This project focuses on making a RISC-V CPU Core using the Logisim software. RISC-V is significant because it will allow smaller device manufacturers to build hardware without paying royalties and allow developers and researchers to design and experiment with a proven and freely available instruction set architecture. RISC-V is ideal for a variety of applications from IOTs to Embedded systems such as disks, CPUs, Calculators, SOCs, etc. RISC-V(Reduced Instruction Set Architecture) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use.
@article{arxiv.2312.01455,
title = {32-Bit RISC-V CPU Core on Logisim},
author = {Siddesh D. Patil and Premraj V. Jadhav and Siddharth Sankhe},
journal= {arXiv preprint arXiv:2312.01455},
year = {2023}
}