WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes

Roberto Giorgi; Gianfranco Mariotti

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes

Hardware Architecture 2025-04-08 v1

Authors: Roberto Giorgi , Gianfranco Mariotti

Abstract

WebRISC-V is a web-based educational tool designed to simulate the pipelined execution of assembly programs according to the RV64IM specifications (64-bit RISC-V processor). The tool allows users to investigate pipeline stalls, understand the internal state of pipeline architectural blocks, and visualize the cycle-by-cycle execution of instructions. WebRISC-V executes directly in a web browser, providing a detailed pipeline execution for RISC-V processors. This paper describes the features of WebRISC-V, compares it with similar tools, and provides an example of its usage in investigating the pipeline.

Keywords

simulation

Cite

@article{arxiv.2504.03722,
  title  = {WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes},
  author = {Roberto Giorgi and Gianfranco Mariotti},
  journal= {arXiv preprint arXiv:2504.03722},
  year   = {2025}
}

Comments

RISC-V Summit Europe, Paris 12-15th May 2025

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