Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted by landmark chips, like the Arm SVE-based Fujitsu A64FX, powering the TOP500 leader Fugaku. The RISC-V V extension has recently reached 1.0-Frozen status. Here, we present its first open-source implementation, discuss the new specification's impact on the micro-architecture of a lane-based design, and provide insights on performance-oriented design of coupled scalar-vector processors. Our system achieves comparable/better PPA than state-of-the-art vector engines that implement older RVV versions: 15% better area, 6% improved throughput, and FPU utilization >98.5% on crucial kernels.
@article{arxiv.2210.08882,
title = {A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design},
author = {Matteo Perotti and Matheus Cavalcante and Nils Wistoff and Renzo Andri and Lukas Cavigelli and Luca Benini},
journal= {arXiv preprint arXiv:2210.08882},
year = {2025}
}
Comments
Accepted version of the article published in "2022 IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)"