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Employing low-resolution analog-to-digital converters (ADCs) for millimeter wave receivers with large antenna arrays provides opportunity to efficiently reduce power consumption of the receiver. Reducing ADC resolution, however, results in…

This work proposes a novel adaptive background compensation scheme for frequency interleaved digital-to-analog converters (FI-DACs). The technique is applicable to high speed digital transceivers such as those used in coherent optical…

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital…

Based on continuously recorded beam positions and corrector excitations from, for example, a closed-orbit feedback system we describe an algorithm that continuously updates an estimate of the orbit response matrix. The speed of convergence…

The quantum charge-coupled device (QCCD) is one of the notable architectures to achieve large-scale trapped-ion quantum computers. To realize QCCD architecture, ions must be transported quickly while minimizing motional excitation.…

High precision and large dynamic range measurement are required in the readout systems for the Water Cherenkov Detector Array (WCDA) in Large High Altitude Air Shower Observatory (LHAASO). This paper presents a prototype of 12-bit 40 MSPS…

Current approaches to fault-tolerant quantum computation will not enable useful quantum computation on near-term devices of 50 to 100 qubits. Leading proposals, such as the color code and surface code schemes, must devote a large fraction…

As ASIC supply voltages approach one volt, the source-impedance goals for power distribution networks are driven ever lower as well. One approach to achieving these goals is to add decoupling capacitors of various values until the desired…

We present a Time-to-Digital Converter (TDC) implemented on a 16 nm Xilinx UltraScale Plus FPGA that achieves a resolution of 1.15 ps, RMS precision of 3.38 ps, a differential nonlinearity (DNL) of [-0.43, 0.24] LSB, and an integral…

Low-resolution analog-to-digital converters (ADCs) are promising for reducing energy consumption and costs of multiuser multiple-input multiple-output (MIMO) systems with many antennas. We propose low-resolution multiuser MIMO receivers…

This paper presents a low hardware consumption, resolution-configurable, automatically calibrating Gray code oscillator time-to-digital converter (TDC) in Xilinx 16nm UltraScale+, 20nm UltraScale and 28nm Virtex-7 field-programmable gate…

With the increasing digital services demand, performance and power-efficiency become vital requirements for digital circuits and systems. However, the enabling CMOS technology scaling has been facing significant challenges of device…

The design of a radiation-hard dual channel 12-bit 40 MS/s pipeline ADC with extended dynamic range is presented, for use in the readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider. The…

Analog to Digital Converters (ADCs) are a major contributor to the energy consumption on the receiver side of millimeter-wave multiple-input multiple-output (MIMO) systems with large antenna arrays. Consequently, there has been significant…

We analyze limited feedback in systems where a multiple-antenna transmitter sends signals to single-antenna receivers with finite-bit ADCs. If channel state information (CSI) is not available with high resolution at the transmitter and the…

In this letter, we investigate the uplink of a reconfigurable intelligent surface (RIS)-aided millimeter-wave (mmWave) multi-user system. In the considered system, however, problems with hardware cost and power consumption arise when…

Low-resolution analog-to-digital converters (ADCs) have emerged as an efficient solution for massive multiple-input multiple-output (MIMO) systems to reap high data rates with reasonable power consumption and hardware complexity. In this…

Low resolution analog-to-digital converters (ADCs) can be employed to improve the energy efficiency (EE) of a wireless receiver since the power consumption of each ADC is exponentially related to its sampling resolution and the hardware…

The use of analog classical systems for computation is generally thought to be a difficult proposition due to the susceptibility of these devices to noise and the lack of a clear framework for achieving fault-tolerance. We present…

A 6bit flash-ADC with 1.2GSps, wide analog bandwidth and low power, realized in a standard digital 0.13 $\mu$m CMOS copper technology is presented. Employing capacitive interpolation gives various advantages when designing for low power: no…