相关论文: A 100 mA Low Voltage Linear Regulators for Systems…
A stable low dropout (LDO) voltage regulator topology is presented in this paper. LDOs are linear voltage regulators that do not produce ripples in the DC voltage. Despite the close proximity of the supply input voltage to the output, this…
This paper presents an output capacitor-less low-dropout regulator (LDO) with a bias switching scheme for biomedical applications with dual-range load currents. Power optimization is crucial for systems with multiple activation modes such…
Demand for on-chip low-dropout regulators (LDOs) with both high power-supply rejection ratio (PSRR) and fast transient response is growing as system-on-chip (SoC) integration increases. However, conventional LDO architectures face…
On-chip voltage regulation using distributed Digital Low Drop Out (LDO) voltage regulators has been identified as a promising technique for efficient power-management for emerging multi-core processors. Digital LDOs (DLDO) can offer low…
The presented paper introduces a design for a phase-locked loop (PLL) that is utilized in frequency synthesis and modulation-demodulation within communication systems and in VLSI applications. The CMOS PLL is designed using 180 nm…
Traditionally, the output noise and power supply rejection of low-dropout regulators (LDOs) are optimized to minimize power supply fluctuations, reducing their impact on the low-frequency noise of target voltage-controlled oscillators…
Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs)…
Nanopositioning techniques currently applied to characterize physical properties of materials interesting for applications at the microscopic scale rely on high-voltage electronic control circuits that should have the lowest possible noise…
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as…
Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and…
Modern applications such as energy harvesting, signal monitoring in bio-medical sensing, portable point of care devices, etc. which involve state of the art mixed signal subsystems require robust ultra low power operation. Here in this…
In MIMO systems, the presence of phase noise is a significant factor that can degrade performance. For MIMO testbeds build from SDR devices, phase noise cannot be ignored, particular in applications that require phase synchronization. This…
This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-um Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5…
This paper presents the design and analysis of a high efficiency, PWM (Pulse-Width-Modulation) Buck converters for mobile phone applications. The steady-state and average-value models for the proposed converter are developed and simulated.…
A universal quantum computer~(QC), though promising ground breaking solutions to complex problems, still faces several challenges with respect to scalability. Current state-of-the-art QC use a great quantity of cables to connect the…
ALDO2 is a multi-function, adjustable, low dropout linear regulator designed in onsemi I3T80 0.35~$\mu$m HV CMOS technology for use in HEP detectors that adopt silicon photomultipliers (SiPMs). The chip features four independent regulators,…
In current MIMO mobile communication systems, phase noise can significantly impair performance. To allow for compensation of these impairments, accurate phase noise modeling is necessary. Numerical modeling of the phase noise process at a…
Standard cells are essential components of modern digital circuit designs. With process technologies advancing toward 2nm, more routability issues have arisen due to the decreasing number of routing tracks, increasing number and complexity…
The main limitation in order to exploit spin torque nano-oscillators (STNOs) in various potential applications is their large phase noise. In this work, we demonstrate its efficient reduction by a highly reconfigurable, compact,…
Recent advances in nanotechnology have enabled researchers to manipulate small collections of quantum mechanical objects with unprecedented accuracy. In semiconductor quantum dot qubits, this manipulation requires controlling the dot…