相关论文: At-Speed Logic BIST for IP Cores

The performance of multiple reconfigurable intelligent surfaces (RISs) receives limited attention in previous studies. This article fills this research gap by investigating the capabilities of multiple RISs in real-world networks. We…

In intelligent transportation systems (ITS), adaptive transit signal priority (TSP) and dynamic bus control systems have been independently developed to maintain efficient and reliable urban bus services. However, those two systems could…

In this study, a novel index modulation based communication system is proposed by combining the recently popular code index modulation-spread spectrum (CIM-SS) and reconfigurable intelligent surface (RIS) techniques. This technique is…

As fault-tolerant quantum computers scale, certifying the accuracy of computations performed with encoded logical qubits will soon become classically intractable. This creates a critical need for scalable, device-independent certification…

In application-specific designs, owing to the trade-off between power consumption and speed, optimization of various circuit parameters has become a challenging task. Several of the performance metrics, viz. energy efficiency, gain,…

In this correspondence, we analyze the performance of a reconfigurable intelligent surface (RIS)-aided communication system that involves a fluid antenna system (FAS)-enabled receiver. By applying the central limit theorem (CLT), we derive…

For robust testing of new technologies used in future, intelligent power and energy systems, realistic testing environments are needed. Due to the dimensions of a real-world environment a field-based installation is often not viable. More…

A technique used to accelerate an adaptive optics simulation platform using reconfigurable logic is described. The performance of parts of this simulation have been improved by up to 600 times (reducing computation times by this factor) by…

Stacked intelligent metasurfaces (SIMs) represent a key enabler for next-generation wireless networks, offering beamforming gains while significantly reducing radio-frequency chain requirements. In conventional space-only SIM architectures,…

We proposes a platform which can generate hardware/software description based on flexible in-struction set architectures (ISAs). The platform takes advantage of the flexibility of field pro-grammable gate array (FPGA) to design many micro…

The Instruction Set Architecture (ISA) defines processor operations and serves as the interface between hardware and software. As an open ISA, RISC-V lowers the barriers to processor design and encourages widespread adoption, but also…

Integrated circuit (IC) piracy and overproduction are serious issues that threaten the security and integrity of a system. Logic locking is a type of hardware obfuscation technique where additional key gates are inserted into the circuit.…

We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of…

High-fidelity two-logical-qubit gates are essential for realizing fault-tolerant quantum computation with bosonic codes, yet experimentally reported fidelities have rarely exceeded 90\%. Here, we propose a geometric phase engineering…

Basic Linear Algebra Subprograms (BLAS) is a core library in scientific computing and machine learning. This paper presents FT-BLAS, a new implementation of BLAS routines that not only tolerates soft errors on the fly, but also provides…

The ``fast iterative shrinkage-thresholding algorithm'', a.k.a. FISTA, is one of the most widely used algorithms in the literature. However, despite its optimal theoretical $O(1/k^2)$ convergence rate guarantee, oftentimes in practice its…

Connecting two surface-code patches may require significantly higher noise at the interface. We show, via circuit-level simulations under a depolarizing noise model with idle errors, that surface codes remain fault tolerant despite…

Efficient machine learning deployment requires models that account for hardware constraints. Because binary logic gates are the fundamental primitives of digital hardware, models built directly from logic operations offer a promising path…

Quantum computers will require encoding of quantum information to protect them from noise. Fault-tolerant quantum computing architectures illustrate how this might be done but have not yet shown a conclusive practical advantage. Here we…

With the potential to provide a clean break from massive multiple-input multiple-output, large intelligent surfaces (LISs) have recently received a thrust of research interest. Various proposals have been made in the literature to define…