相关论文: At-Speed Logic BIST for IP Cores
This paper analyzes the working principle of four-switch cross-shaped reconfigurable intelligent surface (RIS) in detail and reveals the different types of RIS that can be designed based on this structure. Combined with the design examples…
A detection scheme for uplink massive MIMO, dubbed massive-BLAST or M-BLAST, is proposed. The derived algorithm is an enhancement of the well-known soft parallel interference cancellation. Using computer simulations in massive MIMO…
Backscatter communication (BSC) is a promising solution for Internet-of-Things (IoT) connections due to its low-complexity, low-cost, and energy-efficient solution for sensors. There are several network infrastructure setups that can be…
Successive interference cancellation (SIC) is based on the idea that some interfering signals may be strong enough to decode in order to be removed from the aggregate received signal and thus boost performance. In this letter, we study the…
We propose a method to assist fault mitigation in quantum computation through the use of sensors co-located near physical qubits. Specifically, we consider using transition edge sensors co-located on silicon substrates hosting…
We present the bicycle architecture, a modular quantum computing framework based on high-rate, low-overhead quantum LDPC codes identified in prior work. For two specific bivariate bicycle codes with distances 12 and 18, we construct…
The rapid development of Artificial Intelligence (AI) and Internet of Things (IoT) increases the requirement for edge computing with low power and relatively high processing speed devices. The Computing-In-Memory(CIM) schemes based on…
Demonstrating that logical qubits outperform their physical counterparts is a milestone for achieving reliable quantum computation. Here, we propose to protect logical qubits with a novel dynamical decoupling scheme that implements iSWAP…
We present a set of efficiently implementable logical multi-qubit gates in concatenated quantum error correction codes using parity qubits. In particular, we show how fault-tolerant high-weight rotation gates of arbitrary angle can be…
A novel scheme is presented for fault-tolerant quantum computation based on the cluster model. Some relevant logical cluster states are constructed in concatenation by post-selection through verification, without necessity of recovery…
We present concept and implementation of a self-stabilizing Byzantine fault-tolerant distributed clock generation scheme for multi-synchronous GALS architectures in critical applications. It combines a variant of a recently introduced…
Recent research has revealed an ever-growing class of microarchitectural attacks that exploit speculative execution, a standard feature in modern processors. Proposed and deployed countermeasures involve a variety of compiler updates,…
The outsourcing of semiconductor manufacturing raises security risks, such as piracy and overproduction of hardware intellectual property. To overcome this challenge, logic locking has emerged to lock a given circuit using additional key…
Binarized Neural Networks, a recently discovered class of neural networks with minimal memory requirements and no reliance on multiplication, are a fantastic opportunity for the realization of compact and energy efficient inference…
We present introductory considerations and analysis toward computing applications based on the recently introduced deterministic logic scheme with random spike (pulse) trains [Phys. Lett. A 373 (2009) 2338-2342]. Also, in considering the…
Fault-tolerant architectures aim to reduce the noise of a quantum computation. Despite such architectures being well studied a detailed understanding of how noise is transformed in a fault-tolerant primitive such as magic state injection is…
In this paper, we introduce RISP, a reduced instruction spiking processor. While most spiking neuroprocessors are based on the brain, or notions from the brain, we present the case for a spiking processor that simplifies rather than…
Unsatisfiable core analysis can boost the computation of optimum stable models for logic programs with weak constraints. However, current solvers employing unsatisfiable core analysis either run to completion, or provide no suboptimal…
In this paper, we investigate a bistatic multiple-input multiple-output (MIMO) integrated sensing and communication (ISAC) system over block-fading channels, focusing on the scenario where the sensing and communication receivers (Rxs) are…
Multi-device inference can reduce Transformer latency by parallelizing computation. However, existing methods require high inter-device bandwidth, making them impractical for bandwidth-constrained environments. We present ASTRA, a…