相关论文: At-Speed Logic BIST for IP Cores

Reversible logic can provide lower switching energy costs relative to all irreversible logic, including those developed by industry in semiconductor circuits, however, more research is needed to understand what is possible. Superconducting…

We present a formal proof of a time-triggered hardware interface. The design implements the bit-clock synchronization mechanism specified by the FlexRay standard for automotive embedded systems. The design is described at the gate-level. It…

It is becoming increasingly difficult to improve the performance of a a single process (thread) on a computer due to physical limitations. Modern systems use multi-core processors in which multiple processes (threads) may run concurrently.…

The introduction of complex SoCs with multiple processor cores presents new development challenges, such that development support is now a decisive factor when choosing a System-on-Chip (SoC). The presented developments support strategy…

An optimisation algorithm is proposed for designing PID controllers, which minimises the asymptotic open-loop gain of a system, subject to appropriate robust- stability and performance QFT constraints. The algorithm is simple and can be…

We present a physically consistent multiport framework for stacked intelligent metasurfaces (SIMs) with linear and explicit nonlinear terminations. The model provides closed-form input--output relations in the linear case and fixed-point…

Quantum error correction protects fragile quantum information by encoding it into a larger quantum system. These extra degrees of freedom enable the detection and correction of errors, but also increase the operational complexity of the…

This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In…

Reconfigurable intelligent surface (RIS)-based transmission technology offers a promising solution to enhance wireless communication performance cost-effectively through properly adjusting the parameters of a large number of passive…

Universal quantum computers require fault-tolerant logical qudits, as qudits naturally align with the simulation of multi-level physical systems. Here, we present a general framework and working examples for encoding fault-tolerant logical…

In this brief, we set up the finite time stability (FnTSta) theory for dynamical systems with bounded time-varying delays via aperiodically intermittent control (AIC) and quantized control (QC). A more general QC is designed in this brief.…

This paper addresses the monitoring of logic-independent linear-time user-provided properties in multi-threaded component-based systems. We consider intrinsically independent components that can be executed concurrently with a centralized…

The role of inferencing with uncertainty is becoming more important in rule-based expert systems (ES), since knowledge given by a human expert is often uncertain or imprecise. We have succeeded in designing a VLSI chip which can perform an…

Active reconfigurable intelligent surface (RIS) has attracted significant attention as a recently proposed RIS architecture. Owing to its capability to amplify the incident signals, active RIS can mitigate the multiplicative fading effect…

We design and analyze a logical qubit composed of a linear array of electron spins in semiconductor quantum dots. To avoid the difficulty of fully controlling a two-dimensional array of dots, we adapt spin control and error correction to a…

This paper presents a multi-bit reconfigurable intelligent surface (RIS) with a high phase resolution, capable of beam-steering in the azimuthal plane at sub-6 Gigahertz (GHz). Field trials in realistic indoor deployments have been carried…

Reversible logic is gaining interest of many researchers due to its low power dissipating characteristic. In this paper we proposed a new approach for designing online testable reversible circuits. The resultant testable reversible circuit…

As brain-computer interfacing (BCI) systems transition from assistive technology to more diverse applications, their speed, reliability, and user experience become increasingly important. Dynamic stopping methods enhance BCI system speed by…

Logical qubits can be protected from decoherence by performing QEC cycles repeatedly. Algorithms for fault-tolerant QEC must be compiled to the specific hardware platform under consideration in order to practically realize a quantum memory…

In the modern Systems-on-Chip (SoC), the Advanced eXtensible Interface (AXI) protocol exhibits security vulnerabilities, enabling partial or complete denial-of-service (DoS) through protocol-violation attacks. The recent countermeasures…