English

A Novel Fault-Tolerant Logic Style with Self-Checking Capability

Hardware Architecture 2023-06-02 v1 Artificial Intelligence Systems and Control Systems and Control

Abstract

We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of faulttolerant configurable circuits. The AND and OR gates consist of 8 transistors based on CNFET technology, while the proposed XOR gate benefits from both CNFET and low-power MGDI technologies in its transistor arrangement. To demonstrate the feasibility of our new logic gates, we used an AES S-box implementation as the use case. The extensive simulation results using HSPICE indicate that the case-study circuit using on proposed gates has superior speed and power consumption compared to other implementations with error-detection capability

Keywords

Cite

@article{arxiv.2306.00844,
  title  = {A Novel Fault-Tolerant Logic Style with Self-Checking Capability},
  author = {Mahdi Taheri and Saeideh Sheikhpour and Ali Mahani and Maksim Jenihhin},
  journal= {arXiv preprint arXiv:2306.00844},
  year   = {2023}
}

Comments

6 pages, 3 tables, 5 figures

R2 v1 2026-06-28T10:53:34.386Z