数字电路的失效风险分析
离散数学
2013-03-19 v1
摘要
为了分析异步数字电路的失效风险，将时间参数引入布尔代数，用逻辑运算代替算术运算。考虑了一个信号通过逻辑元件的构造示例，使用了下面描述的数学工具。
引用
@article{arxiv.1303.4051,
title = {The failure risk analysis of digital circuits},
author = {A. N. Pchelintsev},
journal= {arXiv preprint arXiv:1303.4051},
year = {2013}
}
备注
In this work there was considered the method of failure risk analysis of digital circuits using an analytic representation of signals within the circuit. At that logical operations had to by replaced by arithmetic operations. The transitions from one signal state to another is described by the Heaviside function