Gain Cell memory (GCRAM) offers higher density and lower power than SRAM, making it a promising candidate for on-chip memory in domain-specific accelerators. To support workloads with varying traffic and lifetime metrics, GCRAM also offers high bandwidth, ultra low leakage power and a wide range of retention times, which can be adjusted through transistor design (like threshold voltage and channel material) and on-the-fly by changing the operating voltage. However, designing and optimizing GCRAM sub-systems can be time-consuming. In this paper, we present OpenGCRAM, an open-source GCRAM compiler capable of generating GCRAM bank circuit designs and DRC- and LVS-clean layouts for commercially available foundry CMOS, while also providing area, delay, and power simulations based on user-specified configurations (e.g., word size and number of words). OpenGCRAM enables fast, accurate, customizable, and optimized GCRAM block generation, reduces design time, ensure process compliance, and delivers performance-tailored memory blocks that meet diverse application requirements.
@article{arxiv.2507.10849,
title = {OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads},
author = {Xinxin Wang and Lixian Yan and Shuhan Liu and Luke Upton and Zhuoqi Cai and Yiming Tan and Shengman Li and Koustav Jana and Peijing Li and Jesse Cirimelli-Low and Thierry Tambe and Matthew Guthaus and H. -S. Philip Wong},
journal= {arXiv preprint arXiv:2507.10849},
year = {2025}
}