4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation

Fuyuki Kihara; Seiji Uenohara; Satoshi Awamura; Naoko Misawa; Chihiro Matsui; Ken Takeuchi

4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation

Hardware Architecture 2025-07-21 v1

Authors: Fuyuki Kihara , Seiji Uenohara , Satoshi Awamura , Naoko Misawa , Chihiro Matsui , Ken Takeuchi

Abstract

Computation-in-Memory (CiM) is attracting attention as a technology that can perform MAC calculations required for AI accelerators, at high speed with low power consumption. However, there is a problem regarding power consumption and device-derived errors that increase as row parallelism increases. In this paper, a 4T2R ReRAM cell and an 8T SRAM CiM suitable for CiM is proposed. It is shown that adopting the proposed 4T2R ReRAM cell reduces the errors due to variation in ReRAM devices compared to conventional 4T4R ReRAM cells.

Keywords

processing-in-memory memristor memory hierarchy

Cite

@article{arxiv.2507.13631,
  title  = {4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation},
  author = {Fuyuki Kihara and Seiji Uenohara and Satoshi Awamura and Naoko Misawa and Chihiro Matsui and Ken Takeuchi},
  journal= {arXiv preprint arXiv:2507.13631},
  year   = {2025}
}

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