SRAM-based compute-in-memory (CIM) offers high computational density and energy efficiency for deep neural network (DNN) accelerators, but its limited capacity causes on/off-chip data movement overhead for large DNN models. Existing CIM accelerator studies typically assume that DNN models fit entirely on-chip, leaving efficient dataflow design largely untapped. This paper introduces AccelCIM, a systematic dataflow exploration framework for SRAM CIM accelerator, which addresses two key limitations of prior work. (1) It formulates a systematic dataflow design space spanning CIM macro configurations and macro-array organizations. (2) It introduces rigorous design evaluation using cycle-accurate architectural simulation and post-layout PPA analysis. We conduct an extensive design space exploration and apply AccelCIM to representative LLM applications, providing practical insights for the principled design of CIM accelerators.
@article{arxiv.2604.17692,
title = {AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator},
author = {Chenhao Xue and Yukun Wang and An Guo and Yuhui Shi and Jinwei Zhou and Xiping Dong and Yihan Yin and Yuanpeng Zhang and Tianyu Jia and Wei Gao and Qiang Wu and Xin Si and Jun Yang and Guangyu Sun},
journal= {arXiv preprint arXiv:2604.17692},
year = {2026}
}