Modern data-intensive applications demand memory solutions that deliver high-density, low-power, and integrated computational capabilities to reduce data movement overhead. This paper presents the use of Gain-Cell embedded DRAM (GC-eDRAM) - a compelling alternative to traditional SRAM and eDRAM - for stateful, in-memory logic. We propose a circuit design that exploits GC-eDRAM's dual-port architecture and nondestructive read operation to perform logic functions directly within the GC-eDRAM memory array. Our simulation results demonstrate a 5us retention time coupled with a 99.5% success rate for computing the logic gates. By incorporating processing-in-memory (PIM) functionality into GC-eDRAM, our approach enhances memory and compute densities, lowers power consumption, and improves overall performance for data-intensive applications.
@article{arxiv.2506.23185,
title = {Stateful Logic In-Memory Using Gain-Cell eDRAM},
author = {Barak Hoffer and Shahar Kvatinsky},
journal= {arXiv preprint arXiv:2506.23185},
year = {2025}
}
Comments
Proceedings of IEEE International NEWCAS Conference, June 2025