The embedded DRAM (eDRAM) is more and more used in System On Chip (SOC). The integration of the DRAM capacitor process into a logic process is challenging to get satisfactory yields. The specific process of DRAM capacitor and the low capacitance value (~30F) of this device induce problems of process monitoring and failure analysis. We propose a new test structure to measure the capacitance value of each DRAM cell capacitor in a DRAM array. This concept has been validated by simulation on a 0.18μm eDRAM technology.
@article{arxiv.0710.4736,
title = {A New Embedded Measurement Structure for eDRAM Capacitor},
author = {L. Lopez and J. M. Portal and D. Nee},
journal= {arXiv preprint arXiv:0710.4736},
year = {2011}
}
Comments
Submitted on behalf of EDAA (http://www.edaa.com/)