This paper describes a multi-functional deep in-memory processor for inference applications. Deep in-memory processing is achieved by embedding pitch-matched low-SNR analog processing into a standard 6T 16KB SRAM array in 65 nm CMOS. Four applications are demonstrated. The prototype achieves up to 5.6X (9.7X estimated for multi-bank scenario) energy savings with negligible (<1%) accuracy degradation in all four applications as compared to the conventional architecture.
@article{arxiv.1610.07501,
title = {A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array},
author = {Mingu Kang and Sujan Gonugondla and Ameya Patil and Naresh Shanbhag},
journal= {arXiv preprint arXiv:1610.07501},
year = {2016}
}