Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC

Hooman Jarollahi; Richard F. Hobson

Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC

Hardware Architecture 2013-02-20 v1 Emerging Technologies

Authors: Hooman Jarollahi , Richard F. Hobson

Abstract

This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM counterparts. This design can be used as cache memory in processors and low-power portable devices. The proposed SRAM cell features ~13% area reduction compared to a conventional 6T cell, and features a unique bit-line and negative supply voltage biasing methodology and ground control architecture to enhance performance, and suppress standby leakage power.

Keywords

CMOS SRAM 5T SRAM dynamic power reduction low-power SoC cache memory bit-line biasing ground control architecture standby leakage

Cite

@article{arxiv.1302.4464,
  title  = {Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC},
  author = {Hooman Jarollahi and Richard F. Hobson},
  journal= {arXiv preprint arXiv:1302.4464},
  year   = {2013}
}

Comments

7 pages, CDES'10 - The 2010 International Conference on Computer Design

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