Achieving brain-like density and performance in neuromorphic computers necessitates scaling down the size of nanodevices emulating neuro-synaptic functionalities. However, scaling nanodevices results in reduction of programming resolution and emergence of stochastic non-idealities. While prior work has mainly focused on binary transitions, in this work we leverage the stochastic switching of a three-state ferroelectric field effect transistor (FeFET) to implement a long-term and short-term 2-tier stochastic synaptic memory with a single device. Experimental measurements are performed on a scaled 28nm high-k metal gate technology-based device to develop a probabilistic model of the hybrid stochastic synapse. In addition to the advantage of ultra-low programming energies afforded by scaling, our hardware-algorithm co-design analysis reveals the efficacy of the 2-tier memory in comparison to binary stochastic synapses in on-chip learning tasks -- paving the way for algorithms exploiting multi-state devices with probabilistic transitions beyond deterministic ones.
@article{arxiv.2209.13685,
title = {Hybrid Stochastic Synapses Enabled by Scaled Ferroelectric Field-effect Transistors},
author = {A N M Nafiul Islam and Arnob Saha and Zhouhang Jiang and Kai Ni and Abhronil Sengupta},
journal= {arXiv preprint arXiv:2209.13685},
year = {2023}
}