Neuromorphic in-memory computing requires area-efficient architecture for seamless and low latency parallel processing of large volumes of data. Here, we report a compact, vertically integrated/stratified field-effect transistor (VSFET) consisting of a 2D non-ferroelectric MoS2 FET channel stacked on a 2D ferroelectric In2Se3 FET channel. Electrostatic coupling between the ferroelectric and non-ferroelectric semiconducting channels results in hysteretic transfer and output characteristics of both FETs. The gate-controlled MoS2 memtransistor is shown to emulate homosynaptic plasticity behavior with low nonlinearity, low epoch, and high accuracy supervised (ANN - artificial neural network) and unsupervised (SNN - spiking neural network) on-chip learning. Further, simultaneous measurements of the MoS2 and In2Se3 transistor synapses help realize complex heterosynaptic cooperation and competition behaviors. These are shown to mimic advanced sensorimotor neural network-controlled gill withdrawal reflex sensitization and habituation of a sea mollusk (Aplysia) with ultra-low power consumption. Finally, we show logic reconfigurability of the VSFET to realize Boolean gates thereby adding significant design flexibility for advanced computing technologies.
@article{arxiv.2412.10757,
title = {Vertically Integrated Dual-memtransistor Enabled Reconfigurable Heterosynaptic Sensorimotor Networks and In-memory Neuromorphic Computing},
author = {Srilagna Sahoo and Abin Varghese and Aniket Sadashiva and Mayank Goyal and Jayatika Sakhuja and Debanjan Bhowmik and Saurabh Lodha},
journal= {arXiv preprint arXiv:2412.10757},
year = {2024}
}