基于二进制搜索和时钟失效检测的宽频率范围内高速锁定与高分辨率混合模式DLL
摘要
本文提出了一种采用二进制搜索（BS）锁定的混合模式延迟锁定回路（MM-DLL），设计覆盖频率范围从533 MHz到4.26 GHz。BS锁定方案优化了锁定时间，将其从线性函数降低为对数函数，完成于B+1个周期内，其中B代表数字到模拟（DAC）分辨率，用于控制电压控制延迟线（VCDL）。在BS过程开始时，较大的步幅可能导致显著的偏置超调，potentially leading to clock failure conditions (i.e., clocks fail to propagate through the VCDL). To address this issue, a toggle detector is introduced to monitor clock activity and adjust the binary search controller. Upon detecting a stalled clock, the controller reverts the DAC code to the previous working code and resumes the BS with a reduced step size. Fabricated in a 3-nm FinFET CMOS process, the proposed MM-DLL achieves a locking time of under 10.5 ns while consuming 5.4 mW from a 0.75 V supply at 4.26 GHz. The measured performance includes a high resolution of 0.73 ps, with a static phase error of 0.73 ps, RMS jitter of 1.2 ps, and peak-to-peak jitter of 4.9 ps. The proposed MM-DLL achieves state-of-the-art power figure of merit (FoM) of 0.82 pJ and DLL locking FoM of 0.01 .
关键词
引用
@article{arxiv.2501.13238,
title = {Fast-Locking and High-Resolution Mixed-Mode DLL with Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS},
author = {Nicolás Wainstein and Eran Avitay and Eugene Avner},
journal= {arXiv preprint arXiv:2501.13238},
year = {2025}
}