相关论文: Fast-Locking and High-Resolution Mixed-Mode DLL wi…

In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency translation range. To achieve this performance, we present a…

In current generation digital phase locked loop (DPLL) architectures, techniques like adaptive loop bandwidth with loop order switching and switched phase-detection are employed to achieve better lock time and jitter performance. This work…

The presented paper introduces a design for a phase-locked loop (PLL) that is utilized in frequency synthesis and modulation-demodulation within communication systems and in VLSI applications. The CMOS PLL is designed using 180 nm…

This paper proposes a novel approach that employs error amplification and ADC-based dual-mixer time-difference (ADC-based-DMTD) technique for high-precision locking of laser repetition frequency with compact size. This electronic system…

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is…

This paper presents a new fast switching hybrid frequency synthesizer with wide locking range. The hybrid synthesizer is based on the tanlock loop with no delay block (NDTL) and is capable of integer as well as fractional frequency…

Fixed-complexity Sphere Decoder (FSD) is a recently proposed technique for Multiple-Input Multiple-Output (MIMO) detection. It has several outstanding features such as constant throughput and large potential parallelism, which makes it…

Dual comb spectroscopy (DCS) is a broadband technique offering high resolution and fast data acquisition. We describe a hybrid dual comb spectrometer comprising a broadband commercial fiber laser system offering a wide range of sample…

A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along…

This work presents the design and preliminary performance of a highly-multiplexed superconducting detector readout. The readout system is implemented on the Xilinx ZCU111 RFSoC Evaluation Board. The current design uses 12% of the DSPs, 60%…

This paper presents a hardware architecture of complex K-best Multiple Input Multiple Output (MIMO) decoder reducing the complexity of Maximum Likelihood (ML) detector. We develop a novel low-power VLSI design of complex K-best decoder for…

A practical deep neural network's (DNN) evaluation involves thousands of multiply-and-accumulate (MAC) operations. To extend DNN's superior inference capabilities to energy constrained devices, architectures and circuits that minimize…

We present an experimental realization of the Optical Frequency Locked Loop (OFLL) applied to long-term frequency difference stabilization of broad-line DFB lasers. The presented design, based on an integrated phase-frequency detector chip,…

Laser synchronization is a technique that locks the wavelength of a free-running laser to that of the reference laser, thereby enabling synchronous changes in the wavelengths of the two lasers. This technique is of crucial importance in…

Large language models (LLMs) show strong potential for neural architecture generation, yet existing approaches produce complete model implementations from scratch -- computationally expensive and yielding verbose code. We propose Delta-Code…

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase or frequency of a cantilever oscillating at…

This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-um Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5…

We experimentally investigate the RF linewidth and timing jitter over a wide range of delay tuning in a self-mode-locked two-section quantum dash lasers emitting at ~ 1.55 micron and operating at ~ 21 GHz repetition rate subject to single…

In this paper, we propose a fast decoder algorithm for uniquely decodable (errorless) code sets for overloaded synchronous optical code-division multiple-access (O-CDMA) systems. The proposed decoder is designed in a such a way that the…

Many-core accelerators are essential for high-performance deep learning, but their performance is undermined by widespread fail-slow failures. Detecting such failures on-chip is challenging, as prior methods from distributed systems are…