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Computing-in-memory (CIM) is renowned in deep learning due to its high energy efficiency resulting from highly parallel computing with minimal data movement. However, current SRAM-based CIM designs suffer from long latency for loading…

Virtual Platforms (VPs) enable early software validation of autonomous systems' electronics, reducing costs and time-to-market. While many VPs support both functional and non-functional simulation (e.g., timing, power), they lack the…

The Advanced Encryption Standard (AES) is a widely adopted cryptographic algorithm essential for securing embedded systems and IoT platforms. However, existing AES hardware accelerators often face limitations in performance, energy…

Hardware Architecture · Computer Science 2025-05-20 Van Tinh Nguyen , Phuc Hung Pham , Vu Trung Duong Le , Hoai Luan Pham , Tuan Hai Vu , Thi Diem Tran

Embedded heterogeneous systems-on-chip (SoCs) rely on domain-specific hardware accelerators to improve performance and energy efficiency. In particular, programmable multi-core accelerators feature a cluster of processing elements and…

Hardware Architecture · Computer Science 2025-02-25 Cyril Koenig , Enrico Zelioli , Luca Benini

Many computer organization and computer architecture classes have recently started adopting the RISC-V architecture as an alternative to proprietary RISC ISAs and architectures. Emulators are a common teaching tool used to introduce…

Programming Languages · Computer Science 2018-12-12 Mihailo Isakov , Michel A. Kinsy

Multi-core vector processor architectures excel in handling computationally intensive vectorizable tasks but struggle to achieve optimal resource utilization when facing sequential and control tasks that cannot be vectorized. This work…

Hardware Architecture · Computer Science 2024-07-09 Matteo Perotti , Michele Raeber , Mattia Sinigaglia , Matheus Cavalcante , Davide Rossi , Luca Benini

Radio Access Networks virtualization (vRAN) is on its way becoming a reality driven by the new requirements in mobile networks, such as scalability and cost reduction. Unfortunately, there is no free lunch but a high price to be paid in…

Networking and Internet Architecture · Computer Science 2023-11-09 J. Xavier Salvat Lozano , Andres Garcia-Saavedra , Xi Li , Xavier Costa-Perez

Structured sparsity has been proposed as an efficient way to prune the complexity of modern Machine Learning (ML) applications and to simplify the handling of sparse data in hardware. The acceleration of ML models - for both training and…

Hardware Architecture · Computer Science 2023-11-14 V. Titopoulos , K. Alexandridis , C. Peltekis , C. Nicopoulos , G. Dimitrakopoulos

Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardware (OSH) platforms offer solutions to issues such as IP costs…

The primary motivation for uptake of virtualization has been resource isolation, capacity management and resource customization allowing resource providers to consolidate their resources in virtual machines. Various approaches have been…

Distributed, Parallel, and Cluster Computing · Computer Science 2010-09-27 Omer Khalid , Ivo Maljevic , Richard Anthony , Miltos Petridis , Kevin Parrot , Markus Schulz

The current challenges in technology scaling are pushing the semiconductor industry towards hardware specialization, creating a proliferation of heterogeneous systems-on-chip, delivering orders of magnitude performance and power benefits…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-02-28 Fares Elsabbagh , Blaise Tine , Priyadarshini Roshan , Ethan Lyons , Euna Kim , Da Eun Shim , Lingjun Zhu , Sung Kyu Lim , Hyesoon kim

WebRISC-V is a web-based educational tool designed to simulate the pipelined execution of assembly programs according to the RV64IM specifications (64-bit RISC-V processor). The tool allows users to investigate pipeline stalls, understand…

Hardware Architecture · Computer Science 2025-04-08 Roberto Giorgi , Gianfranco Mariotti

Ensuring a continuous and growing influx of skilled chip designers and a smooth path from education to innovation are key goals for several national and international "Chips Acts". Silicon democratization can greatly benefit from end-to-end…

Systolic arrays and shared-L1-memory manycore clusters are commonly used architectural paradigms that offer different trade-offs to accelerate parallel workloads. While the first excel with regular dataflow at the cost of rigid…

Hardware Architecture · Computer Science 2024-04-25 Sergio Mazzola , Samuel Riedel , Luca Benini

The last few years have seen the emergence of IoT processors: ultra-low power systems-on-chips (SoCs) combining lightweight and flexible micro-controller units (MCUs), often based on open-ISA RISC-V cores, with application-specific…

Systems and Control · Electrical Eng. & Systems 2022-01-21 Nazareno Bruschi , Germain Haugou , Giuseppe Tagliavini , Francesco Conti , Luca Benini , Davide Rossi

Vehicle-to-vehicle (V2V) communication is a crucial component of the future autonomous driving systems since it enables improved awareness of the surrounding environment, even without extensive processing of sensory information. However,…

Networking and Internet Architecture · Computer Science 2017-01-12 Vladimir Savic , Elad M. Schiller , Marina Papatriantafilou

Traditionally, HPC workloads have been deployed in bare-metal clusters; but the advances in virtualization have led the pathway for these workloads to be deployed in virtualized clusters. However, HPC cluster administrators/providers still…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-06-24 Jashwant Raj Gunasekaran , Michael Cui , Prashanth Thinakaran , Josh Simons , Mahmut Taylan Kandemir , Chita R. Das

As OS-level virtualization technology usually imposes little overhead on virtual machine start-up and running, it provides an excellent choice for building intrusion/fault tolerant applications that require redundancy and frequent…

Operating Systems · Computer Science 2016-09-16 Zhiyong Shan , Yang Yu , Tzi-cker Chiueh

While Transformers are dominated by Floating-Point (FP) Matrix-Multiplications, their aggressive acceleration through dedicated hardware or many-core programmable systems has shifted the performance bottleneck to non-linear functions like…

Hardware Architecture · Computer Science 2025-04-16 Run Wang , Gamze Islamoglu , Andrea Belano , Viviane Potocnik , Francesco Conti , Angelo Garofalo , Luca Benini

As the complexity and scale of modern parallel machines continue to grow, programmers increasingly rely on composition of software libraries to encapsulate and exploit parallelism. However, many libraries are not designed with composition…