Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardware (OSH) platforms offer solutions to issues such as IP costs and vendor dependency. Existing multi-core cache-coherent RISC-V platforms are complex and not efficient for small embedded core clusters. We propose an open-source SystemVerilog implementation of a lightweight snoop-based cache-coherent cluster of Linux-capable CVA6 cores. Our design uses the MOESI protocol via the Arm's AMBA ACE protocol. Evaluated with Splash-3 benchmarks, our solution shows up to 32.87% faster performance in a dual-core setup and an average improvement of 15.8% over OpenPiton. Synthesized using GF 22nm FDSOI technology, the Cache Coherency Unit occupies only 1.6% of the system area.
@article{arxiv.2407.19895,
title = {Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor},
author = {Riccardo Tedeschi and Luca Valente and Gianmarco Ottavi and Enrico Zelioli and Nils Wistoff and Massimiliano Giacometti and Abdul Basit Sajjad and Luca Benini and Davide Rossi},
journal= {arXiv preprint arXiv:2407.19895},
year = {2024}
}
Comments
4 pages, 4 figures, DSD2024 and SEAA2024 Works in Progress Session AUG 2024; Updated the acknowledgments