Heterogeneous, multicore SoC architectures are a critical component of today's computing landscape. However, supporting both increasing heterogeneity and multicore execution are significant design challenges. Meanwhile, the growing RISC-V and open-source hardware (OSH) movements have resulted in an increased number of open-source RISC-V processor implementations; however, there are fewer open source SoC design platforms that integrate these processor cores. We present modifications to ESP, an open-source SoC design platform, to enable multicore execution with the RISC-V CVA6 processor. Our implementation is modular and based on standardized interfaces. These properties simplify the integration of new cores. Our modifications enable RISC-V-based SoCs designed with ESP for FPGA to boot Linux SMP and execute multithreaded applications. Coupled with ESP's emphasis on accelerator-centric architectures, our contributions enable the seamless design of a wide range of heterogeneous, multicore SoCs.
@article{arxiv.2206.01901,
title = {Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP},
author = {Joseph Zuckerman and Paolo Mantovani and Davide Giri and Luca P. Carloni},
journal= {arXiv preprint arXiv:2206.01901},
year = {2022}
}
Comments
To appear in the Sixth Workshop on Computer Architecture Research with RISC-V (CARRV 2022)