Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6

Umberto Laghi; Simone Manoni; Emanuele Parisi; Andrea Bartolini

Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6

Hardware Architecture 2025-04-04 v1

Authors: Umberto Laghi , Simone Manoni , Emanuele Parisi , Andrea Bartolini

Abstract

In this work, we present the design and evaluation of a Processor Tracing System compliant with the RISC-V Efficient Trace specification for Instruction Branch Tracing. We integrate our system into the host domain of a state-of-the-art edge architecture based on CVA6. The proposed Tracing System introduces a total overhead of 9.2% in terms of resource utilization on a Xilinx VCU118 FPGA on the CVA6 subsystem while achieving an average compression rate of 95.1% on platform-specific tests, compared to tracing each full opcode instruction.

Keywords

computer architecture fpga accelerator

Cite

@article{arxiv.2504.01972,
  title  = {Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6},
  author = {Umberto Laghi and Simone Manoni and Emanuele Parisi and Andrea Bartolini},
  journal= {arXiv preprint arXiv:2504.01972},
  year   = {2025}
}

Comments

2 pages, 2 figures, 1 table, accepted at RISC-V Summit Europe 2025

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