Using a Performance Model to Implement a Superscalar CVA6

Côme Allart; Jean-Roch Coulon; André Sintzoff; Olivier Potin; Jean-Baptiste Rigaud

Using a Performance Model to Implement a Superscalar CVA6

Hardware Architecture 2024-10-03 v1

Authors: Côme Allart , Jean-Roch Coulon , André Sintzoff , Olivier Potin , Jean-Baptiste Rigaud

Abstract

A performance model of CVA6 RISC-V processor is built to evaluate performance related modifications before implementing them in RTL. Its accuracy is 99.2% on CoreMark. This model is used to evaluate a superscalar feature for CVA6. During design phase, the model helped detecting and fixing performance bugs. The superscalar feature resulted in a CVA6 performance improvement of 40% on CoreMark.

Keywords

computer architecture

Cite

@article{arxiv.2410.01442,
  title  = {Using a Performance Model to Implement a Superscalar CVA6},
  author = {Côme Allart and Jean-Roch Coulon and André Sintzoff and Olivier Potin and Jean-Baptiste Rigaud},
  journal= {arXiv preprint arXiv:2410.01442},
  year   = {2024}
}

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