Related papers: A 4.9-GHz Low Power, Low Jitter, LC Phase Locked L…

A novel design for a low dropout (LDO) voltage regulator is presented and dedicated to power many sections of a typical cellular handset. However, these baseband, RF, and audio sections have different requirements that influence which LDO…

This paper presents a low-jitter hybrid voltage level shifter (HVLS) suitable for high-speed applications. The proposed architecture offers the advantage of cross-coupled feedback to simultaneously generate two voltage domain signals with…

Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs)…

In a phase-locked loop (PLL) synchronized inverter, due to the strong nonlinear coupling between the PLL's parame-ters and the operation power angle, the equivalent damping coefficient will quickly deteriorate while the power angle is close…

This article explains phase noise, jitter, and some slower phenomena in digital integrated circuits, focusing on high-demanding, noise-critical applications. We introduce the concept of phase type and time type phase noise. The rules for…

Charge pump phase-locked loop with phase-frequency detector (CP-PLL) is an electrical circuit, widely used in digital systems for frequency synthesis and synchronization of the clock signals. In this paper a non-linear second-order model of…

Low cost, small footprint, highly efficient and mass producible on-chip wavelength-division-multiplexing (WDM) light sources are key components in future silicon electronic and photonic integrated circuits (EPICs) which can fulfill the…

This paper presents a switch-type attenuator working from 20 to 100 GHz. The attenuator adopts a capacitive compensation technique to reduce phase error. The small resistors in this work are implemented with metal lines to reduce the…

Power dissipation in integrated circuits is one of the major concerns to the research community, at the verge when more number of transistors are integrated on a single chip. The substantial source of power dissipation in sequential…

We report a single-frequency, narrow-linewidth semiconductor pulsed laser based on pump current modulation and optical injection locking technique. A monolithic non-planar ring oscillator laser is employed as the seed source to guarantee…

Phase locking experiments on vortex based spin transfer oscillators with an external microwave current are performed. We present clear evidence of phase locking, frequency pulling, as well as fractional synchronization in this system, with…

This paper presents a mixed-mode delay-locked loop (MM-DLL) with binary search (BS) locking, designed to cover a broad frequency range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to…

Grid-interactive power converters are normally synchronized to the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations…

We develop a compact four-port superconducting switch with a tunable operating frequency in the range of 4.8 GHz -- 7.3 GHz. Isolation between channel exceeds 20~dB over a bandwidth of several hundred megahertz, exceeding 40 dB at some…

We present LUCAS (Low power Ultra-low jitter Compact ASIC for SiPM), an analog front-end for Silicon Photomultipliers (SiPM) targeting fast timing detectors in Time-of-Flight Computed Tomography (ToF-CT). LUCAS features a very low input…

The main limitation in order to exploit spin torque nano-oscillators (STNOs) in various potential applications is their large phase noise. In this work, we demonstrate its efficient reduction by a highly reconfigurable, compact,…

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves…

This paper presents the analysis, design, fabrication, and measurement of an integrated low-noise amplifier (LNA) implemented using a 130 nm CMOS technology, operating in the 2.4 GHz band. The LNA is a crucial component in the performance…

This article describes the design methodology to achieve reflective diode-based parametric frequency selective limiters (pFSLs) with low power thresholds ($P_{th}$) and sub-dB insertion-loss values ($IL^{s.s}$) for driving power levels…

We demonstrate 14.3-attosecond timing jitter [integrated from 10 kHz to 94 MHz offset frequency] optical pulse trains from 188-MHz repetition-rate mode-locked Yb-fiber lasers. In order to minimize the timing jitter, we shorten the non-gain…