Related papers: A 4.9-GHz Low Power, Low Jitter, LC Phase Locked L…
An e+e- linear collider at 500-GeV C.M. (center of mass) has been proposed as a future accelerator. The C-band linear collider has more than a thousand klystrons and matching modulators. The linear colliders require smart modulators with…
Public Safety Power Shutoffs (PSPS) force rapid topology changes that can render standard operating points infeasible, requiring operators to quickly identify corrective transmission switching actions that reduce load shedding while…
The NA62 experiment is designed to measure the ultra-rare decay $K^+ \rightarrow \pi^+ \nu \bar{\nu}$ branching ratio with a precision of $\sim 10\%$ at the CERN Super Proton Synchrotron (SPS). The trigger system of NA62 consists in three…
In this paper we discuss the application of the harmonic balance method for the global analysis of the classical phase-locked loop (PLL) circuit. The harmonic balance is non rigorous method, which is widely used %,often without rigorous…
We demonstrate a design for a high-performance $2 \times 2$ splitter meeting the essential requirements of broadband coupling, support for arbitrary coupling ratio, ultra low-loss, high fabrication tolerance, and a compact footprint. This…
Novel non-volatile memory devices based on ferroelectric thin films represent a promising emerging technology that is ideally suited for neuromorphic applications. The physical switching mechanism in such films is the nucleation and growth…
This article presents a reconfigurable physically unclonable function (PUF) design fabricated using 65-nm CMOS technology. A subthreshold-inverter-based static PUF cell achieves 0.3% native bit error rate (BER) at 0.062-fJ per bit core…
We demonstrate absorber-free passive and hybrid mode-locking at sub-GHz repetition rates using a hybrid integrated extended cavity diode laser around 1550 nm. The laser is based on InP as gain medium and a long Si$_3$N$_4$ feedback circuit,…
In the present work, a second-order type 2 PLL with a piecewise-linear phase detector characteristic is analysed. An exact solution to the Gardner problem on the lock-in range is obtained for the considered model. The solution is based on a…
This paper describes several new algorithms for estimating the parameters of a periodic bandlimited signal from samples corrupted by jitter (timing noise) and additive noise. Both classical (non-random) and Bayesian formulations are…
Next-generation cellular systems require low-power mm-wave phased-array ICs. Variable-gain LNAs (VG-LNAs) are key blocks enabling reduced hardware complexity, performance improvement and added functionalities. This paper reports a low-power…
We present a power efficient clock-less fully asynchronous bit-serial Low Voltage Differential Signaling (LVDS) link with event-driven instant wake-up and self-sleep features, optimized for high speed inter-chip communication of…
This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter…
We present a scheme to phase-lock a 240 mW, 852 nm distributed Bragg reflector (DBR) laser to a fixed-frequency narrow-linewidth laser with a rapidly tunable frequency offset near 9 GHz. The phase-lock is accomplished by electronic feedback…
We experimentally study the phase stabilization of a semiconductor double quantum dot (DQD) single atom maser by injection locking. A voltage-biased DQD serves as an electrically tunable microwave frequency gain medium. The statistics of…
Although modern FPGAs have a performance potential of a 1 GHz clock frequency - with both clock networks and embedded blocks such as memories and DSP Blocks capable of these clock rates - user implementations approaching this speed are…
During the pulsed operation of the linear accelerator in DCLS (Dalian Coherent Light Source), we found a strong correlation between the klystron modulator's high voltage and the klystron output microwave, with noticeable jitter among…
An earlier study of a high layer-count test board using plated-through-hole (PTH) vias and a limited quantity of laser vias was shown to be capable of supporting 112 Gb/s PAM-4 links (or equivalent signaling having 28 GHz (Nyquist)…
Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable…
This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed…