Related papers: A 4.9-GHz Low Power, Low Jitter, LC Phase Locked L…

The presented paper introduces a design for a phase-locked loop (PLL) that is utilized in frequency synthesis and modulation-demodulation within communication systems and in VLSI applications. The CMOS PLL is designed using 180 nm…

The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25 um Silicon-on-Sapphire…

In this paper, we demonstrate a simple scheme of 6.835 GHz microwave frequency synthesizer based on the sub-sampling phase lock loop (PLL) technique. The application of the sub-sampling PLL is the key to simplify the architecture of the…

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power…

Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and…

In current generation digital phase locked loop (DPLL) architectures, techniques like adaptive loop bandwidth with loop order switching and switched phase-detection are employed to achieve better lock time and jitter performance. This work…

This paper presents a low-loss optically-controlled inline RF switch suitable for L- and S-band applications. Under 1.5 W laser power, the switch exhibits a measured ON-state insertion loss of less than 0.33 dB and return loss better than…

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in 65 nm CMOS technology. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are…

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of…

In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency translation range. To achieve this performance, we present a…

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is…

Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps…

Modern communication and computer systems require rapid (Gbps), efficient and large bandwidth data transfers. Agressive scaling of digital integrated systems allow buses and communication controller circuits to be integrated with the…

Radiation tolerant, high speed and low power serializer ASIC is critical for optical link systems in particle physics experiments. Based on a commercial 0.25 um silicon-on-sapphire CMOS technology, we design a 16:1 serializer with 5 Gbps…

A 20 GHz LLRF system is being built using a two-board(RF Front End + ADC/DAC/FPGA) architecture. The RF Front End provides 8 down-converting channels and 3 up-converting channels (5.5-20 GHz RF to 0.05-3 GHz IF). Separate, phase locked,…

We introduce the world's first SPAD family design in 130 nm SiGe BiCMOS process. At 1.8um, we achieved the smallest pitch on record thanks to guard-ring sharing techniques, while keeping a relatively high fill factor of 24.2%. 4x4 SPAD…

We consider a grid-connected voltage source converter (VSC) and address the problem of estimating the grid angle and frequency, information that is essential for an appropriate operation of the converter. We design phase-locked loop (PLL)…

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase or frequency of a cantilever oscillating at…

We report a non-blocking high-resolution digital delay line based on an asynchronous circuit design. Field programmable gate array logic primitives were used as a source of delay and optimally arranged using combinatorial optimization. This…

In current MIMO mobile communication systems, phase noise can significantly impair performance. To allow for compensation of these impairments, accurate phase noise modeling is necessary. Numerical modeling of the phase noise process at a…