The Design of a High Speed Low Power Phase Locked Loop

Tiankuan Liu; Datao Gong; Suen Hou; Zhihua Liang; Chonghan Liu; Da-Shung Su; Ping-Kun Teng; Annie C. Xiang; Jingbo Ye

doi:10.5170/CERN-2009-006.476

The Design of a High Speed Low Power Phase Locked Loop

Instrumentation and Detectors 2024-01-31 v1

Authors: Tiankuan Liu , Datao Gong , Suen Hou , Zhihua Liang , Chonghan Liu , Da-Shung Su , Ping-Kun Teng , Annie C. Xiang , Jingbo Ye

View on arXiv ↗ PDF ↗ DOI ↗

Abstract

The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25 um Silicon-on-Sapphire (SoS) CMOS technology. Post-layout simulation indicates that tuning range is 3.79-5.01 GHz and power consumption is 104 mW. The PLL has been submitted for fabrication. The design and simulation results are presented.

Keywords

phase locked loop high speed low power serializer ASIC ATLAS Liquid Argon Calorimeter silicon-on-sapphire CMOS

Cite

@article{arxiv.2401.16681,
  title  = {The Design of a High Speed Low Power Phase Locked Loop},
  author = {Tiankuan Liu and Datao Gong and Suen Hou and Zhihua Liang and Chonghan Liu and Da-Shung Su and Ping-Kun Teng and Annie C. Xiang and Jingbo Ye},
  journal= {arXiv preprint arXiv:2401.16681},
  year   = {2024}
}

Comments

5 pages, 13 figures, Proceedings of the Topical Workshop on Electronics for Particle Physics 2009

The Design of a High Speed Low Power Phase Locked Loop

Abstract

Keywords

Cite

Comments

Related papers