An Integer-N Frequency Synthesizer for Flexible On-Chip Clock Generation
Signal Processing
2025-01-16 v2 High Energy Physics - Experiment
Abstract
A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in 65 nm CMOS technology. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked a 10-50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. Experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.
Cite
@article{arxiv.2411.01552,
title = {An Integer-N Frequency Synthesizer for Flexible On-Chip Clock Generation},
author = {Soumyajit Mandal and Piotr Maj and Grzegorz W. Deptuch},
journal= {arXiv preprint arXiv:2411.01552},
year = {2025}
}
Comments
Under review for publication in JINST