Related papers: An Integer-N Frequency Synthesizer for Flexible On…

The presented paper introduces a design for a phase-locked loop (PLL) that is utilized in frequency synthesis and modulation-demodulation within communication systems and in VLSI applications. The CMOS PLL is designed using 180 nm…

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is…

This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-um Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5…

In this paper, we demonstrate a simple scheme of 6.835 GHz microwave frequency synthesizer based on the sub-sampling phase lock loop (PLL) technique. The application of the sub-sampling PLL is the key to simplify the architecture of the…

We report on the development and phase noise performance of a 9.1926 GHz microwave frequency synthesizer to be used as the local oscillator for a Cs fountain clock. It is based on frequency multiplication and synthesis from an ultralow…

This paper presents a new fast switching hybrid frequency synthesizer with wide locking range. The hybrid synthesizer is based on the tanlock loop with no delay block (NDTL) and is capable of integer as well as fractional frequency…

Phase noise of the frequency synthesizer is one of the main limitations to the short-term stability of microwave atomic clocks. In this work, we demonstrated a low-noise, simple-architecture microwave frequency synthesizer for a coherent…

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power…

Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs)…

Integrated-photonics microchips now enable a range of advanced functionalities for high-coherence applications such as data transmission, highly optimized physical sensors, and harnessing quantum states, but with cost, efficiency, and…

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of…

Power dissipation in integrated circuits is one of the major concerns to the research community, at the verge when more number of transistors are integrated on a single chip. The substantial source of power dissipation in sequential…

As the demand for high-performance microprocessors increases, the circuit complexity and the rate of data transfer increases resulting in higher power consumption. We propose a clocking architecture that uses a series LC resonance and…

This paper presents the analysis, design, fabrication, and measurement of an integrated low-noise amplifier (LNA) implemented using a 130 nm CMOS technology, operating in the 2.4 GHz band. The LNA is a crucial component in the performance…

The upgrade of ATLAS Liquid Argon Calorimeter (LAr) Phase-1 trigger requires high-speed, low-latency data transmission to read out the Lar Trigger Digitizer Board (LTDB). A dual-channel transmitter ASIC LOCx2 have been designed and…

This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS…

We present hardware/software techniques to intelligently regulate supply voltage and clock frequency of intermittently-computing devices. These devices rely on ambient energy harvesting to power their operation and small capacitors as…

On a chassis of gear model, we have offered a quantitative description for our method to synthesize a chemical clock signal with various duty cycles in Part I. As Part II of the study, this paper devotes itself in proposing a design…

Power dissipation in the sequential systems of modern CPU integrated chips (CPU-IC viz., Silicon Chip) is in discussion since the last decade. Researchers have been cultivating many low power design methods to choose the best potential…

Passive and linear nonreciprocal networks at microwave frequencies hold great promises in enabling new front-end architectures for wireless communication systems. Their nonreciprocity has been achieved by disrupting the time-reversal…