Plated-Through-Hole Via Design Specifications for 112G Serial Links

Michael J. Degerstrom; Chad M. Smutzer; Richard B. Ericson; Clifton R Haider; Barry K. Gilbert

Plated-Through-Hole Via Design Specifications for 112G Serial Links

Networking and Internet Architecture 2023-04-05 v1 Signal Processing

Authors: Michael J. Degerstrom , Chad M. Smutzer , Richard B. Ericson , Clifton R Haider , Barry K. Gilbert

Abstract

An earlier study of a high layer-count test board using plated-through-hole (PTH) vias and a limited quantity of laser vias was shown to be capable of supporting 112 Gb/s PAM-4 links (or equivalent signaling having 28 GHz (Nyquist) bandwidth). This original board design was then rebuilt using a different fabricator, and the test results revealed a significant decrease in the bandwidth of the vias. These results led to the development of a set of design specifications that PCB vendors can easily validate, which will ensure that the use of high layer-count boards with PTH technology are viable for emerging 112 Gb/s PAM-4 links.

Keywords

plated-through-hole via 112g pam-4 serial link pcb design via bandwidth signal integrity

Cite

@article{arxiv.2304.01913,
  title  = {Plated-Through-Hole Via Design Specifications for 112G Serial Links},
  author = {Michael J. Degerstrom and Chad M. Smutzer and Richard B. Ericson and Clifton R Haider and Barry K. Gilbert},
  journal= {arXiv preprint arXiv:2304.01913},
  year   = {2023}
}

Comments

20 pages, 16 figures, DesignCon 2017

Plated-Through-Hole Via Design Specifications for 112G Serial Links

Abstract

Keywords

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