Related papers: Non-Hysteretic Condition in Negative Capacitance J…
In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of…
In this paper, we take a fresh look at the physics and operation of Negative Capacitance FETs, and provide unambiguous feedback to the device designers by examining NC-FETs' design space for sub-60 mV/dec Subthreshold Swing (SS).…
The study investigates the influence of negative capacitance on the transfer characteristics of vdW FETs on the heterophase of CIPS ferroelectric. Notably, a less pronounced NC resulting from the spatial distribution of the ferroelectric…
This paper presents a generalization of the charge-based model for ultrathin junctionless double-gate (JLDG) field-effect transistors (FETs) by including quantum electron density. The analytical derivation relies on a first-order correction…
Negative capacitance can be used to overcome the lower limit of subthreshold swing (SS) in field effect transistors (FETs), enabling ultralow-power microelectronics, though the concept of ferroelectric negative capacitance remains…
We report on measurements and modeling of FE HfZrO/SiO2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that many of the phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain…
Heat capacity measurements on the prototypical three-dimensional random-field Ising model compound Fe0.58Zn0.42F2 have been performed in both of the field-cooling (FC) and zero-field-cooling (ZFC) procedures. There is no evidence of…
We present a thorough analysis of the foundations of models of stabilization of negative capacitance (NC) in a ferroelectric (FE) layer by capacitance matching to a dielectric layer, which claim that the FE is stabilized in a low…
Steep-slope $\beta$-Ga$_2$O$_3$ nano-membrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in gate dielectric stack. Subthreshold slope less than 60 mV/dec at room…
In this paper we revisit the theory of negative capacitance, in a (i) standalone ferroelectric, (ii) ferroelectric-dielectric, and (iii) ferroelectric-semiconductor series combination, and show that it is important to minimize the total…
The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the gate has attracted much attention. Recently, we modeled this effect in the…
Integrated circuits (ICs) that can operate at high temperature have a wide variety of applications in the fields of automotive, aerospace, space exploration, and deep-well drilling. Conventional silicon-based complementary…
In this paper, an analytical predictive model of interface charge traps in symmetric long channel double-gate junctionless transistors is proposed based on a charge-based model. Interface charge traps arising from the exposure to chemicals,…
Junctionless Nanowire Field-Effect Transistors (JNFETs), where the channel region is uniformly doped without the need for source-channel and drain-channel junctions or lateral doping abruptness, are considered an attractive alternative to…
We analyse hysteresis in a one-dimensional anti-ferromagnetic random field Ising model at zero-temperature. The random field is taken to have a rectangular distribution of width $2 \Delta$ centered about the origin. A uniform applied field…
We analyze the thermodynamic properties of the spin-S two-dimensional quantum Heisenberg antiferromagnet on a square lattice with nearest and next-nearest neighbor couplings in the Neel phase (J_2/J_1<0.4) employing the quantum hierarchical…
We experimentally investigate capacitance response of a thick ferroelectric GeTe single-crystal flake on the Si/SiO2 substrate, where p-doped Si layer serves as a gate electrode. We confirm by resistance measurements, that for…
This brief proposes an analytical approach to model the dc electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistor (JLNW-FET). The model includes explicit expressions, taking into account the…
Recent results on the gapless 2SC phase are reviewed. These include: the thermal stability under the constraint of the local charge neutrality condition, the properties at zero and nonzero temperatures, and the color screening properties.
Negative capacitance (NC) in ferroelectrics, which stems from the imperfect screening of polarization, is considered a viable approach to lower voltage operation in the field-effect transistors (FETs) used in logic switches. In this paper,…