Related papers: 20 GHZ Low Noise LLRF System

A monolithic multi-channel analog transient recorder, implemented using switched capacitor sample-and-hold circuits and a high-speed analogically-adjustable delay-line-based write clock, has been designed, fabricated and tested. The 2.1 by…

In this paper, the field programmable gate array (FPGA) implementation of a fetal heart rate (FHR) monitoring system is presented. The system comprises of a preprocessing unit to remove various types of noise, followed by a fetal…

This paper presents significant frequency scaling of acoustic filter technology to 50 GHz. This achievement is enabled by the P3F LiNbO3 multilayer stack, in which piezoelectric thin-films of alternating orientations are transferred in…

This paper proposes a complete IFoF system architecture derived from simplified IEEE802.15.3c PHY layer proposal to successfully ensure near 1 Gbps on the air interface. The system architecture utilizes low complexity baseband processing…

To asses stability against 1/f noise, the Low Frequency Instrument (LFI) onboard the Planck mission will acquire data at a rate much higher than the data rate allowed by its telemetry bandwith of 35.5 kbps. The data are processed by an…

This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed…

This paper presents a partially parallel low-density parity-check (LDPC) decoder designed for the 5G New Radio (NR) standard. The design is using a multi-block parallel architecture with a flooding schedule. The decoder can support any code…

We demonstrate ultralow phase noise 10-GHz microwave signal generation from a free-running mode-locked Er-fiber laser with -142 and -157 dBc/Hz single-sideband absolute phase noise at 10- and 100-kHz offset frequencies, respectively. The…

Building upon existing signal processing techniques and open-source software, this paper presents a baseline design for an RF System-on-Chip Frequency Division Multiplexed readout for a spatio-spectral focal plane instrument based on low…

In this article it is presented an FPGA based $M$ulti-$V$oltage $T$hreshold (MVT) system which allows of sampling fast signals ($1-2$ ns rising and falling edge) in both voltage and time domain. It is possible to achieve a precision of time…

This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter…

A low level radio frequency (LLRF) control system is designed and constructed at Peking University, which is for the DC-SRF photo injector operating at 2K. Besides with continuous wave (CW), the system is also reliable with pulsed RF and…

This paper presents an output capacitor-less low-dropout regulator (LDO) with a bias switching scheme for biomedical applications with dual-range load currents. Power optimization is crucial for systems with multiple activation modes such…

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves…

Guiding and manipulating GHz frequency acoustic waves in $\mu$m-scale waveguides and resonators opens up new degrees of freedom to manipulate radio frequency (RF) signals in chip-scale platforms. A critical requirement for enabling…

Demand for on-chip low-dropout regulators (LDOs) with both high power-supply rejection ratio (PSRR) and fast transient response is growing as system-on-chip (SoC) integration increases. However, conventional LDO architectures face…

In the context of the Galactic Emission Mapping, a new receiver at 5GHz was developed to characterize the galactic foreground to the Cosmic Microwave Background Radiation. This is a 5GHz super heterodyne polarimeter with double down…

Ultra-low latency, the hallmark of fifth-generation mobile communications (5G), imposes exacting timing demands on identification as well. Current cryptographic solutions introduce additional computational overhead, which results in…

The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25 um Silicon-on-Sapphire…

In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pin-compatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in a 0.25-um Silicon-on-Sapphire CMOS process and each channel operates at 5.12…