Related papers: 20 GHZ Low Noise LLRF System

This work presents the design, fabrication, and testing of X-Cut Lithium Niobate (LN) acoustic nanoelectromechanical (NEMS) Laterally Vibrating Resonators (LVRs) and Degenerate LVRs (d-LVRs) operating in the S0 (YZ30) and SH0 (YZ-10) modes…

We present computational studies on a proposed 20 by 20 elements electronically reconfigurable liquid crystal (LC) based binary phase reflectarray metasurface, operational at 108 GHz. LC was modelled after Mer's GT3-23001, and full wave…

This paper presents a switch-type attenuator working from 20 to 100 GHz. The attenuator adopts a capacitive compensation technique to reduce phase error. The small resistors in this work are implemented with metal lines to reduce the…

We report on the design, fabrication and testing of a set of high performance corrugated feed horns at 30 GHz, 70 GHz and 100 GHz, built as advanced prototypes for the Low Frequency Instrument (LFI) of the ESA Planck mission. The…

Acoustic filters are preferred front-end solutions at sub-6 GHz due to their superior frequency selectivity compared to electromagnetic (EM) counterparts. With the ongoing development of 5G and the evolution toward 6G, there is a growing…

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in 65 nm CMOS technology. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are…

This work demonstrates the first non-reciprocal network based on switched low-loss acoustic delay lines. The 4-port circulator is built upon a recently reported frequency-independent, programmable, non-reciprocal framework based on switched…

We present a novel low latency CMOS hardware accelerator for fully connected (FC) layers in deep neural networks (DNNs). The FC accelerator, FC-ACCL, is based on 128 8x8 or 16x16 processing elements (PEs) for matrix-vector multiplication,…

In this paper we describe a single-node, double precision Field Programmable Gate Array (FPGA) implementation of the Conjugate Gradient algorithm in the context of Lattice Quantum Chromodynamics. As a benchmark of our proposal we invert…

We have developed a completely new type of general-purpose CCD data acquisition system which enables one to drive any type of CCD using any type of clocking mode. A CCD driver system widely used before consisted of an analog multiplexer…

Networks on Chip is a recent solution paradigm adopted to increase the performance of Multicore designs. The key idea is to interconnect various computation modules (IP cores) in a network fashion and transport packets simultaneously across…

We present a control and measurement setup for superconducting qubits based on Xilinx 16-channel radio-frequency system-on-chip (RFSoC) device. The proposed setup consists of four parts: multiple RFSoC boards, a setup to synchronise every…

Waveform feature is one of the requirements for the FRIB LLRF controllers. It is desired that the LLRF con-trollers store the internal data (e.g. the amplitude and phase information of forward/reverse/cavity signals) for at least one second…

This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered…

The China initiative Accelerator Driven System, CiADS, physics design adopts $162.5 \,\mathrm{MHz}$, $325 \,\mathrm{MHz}$, and $650 \,\mathrm{MHz}$ cavities, which are driven by the corresponding radio frequency (RF) power system, requiring…

The low level rf (LLRF) control system for the rapid cycling synchrotron (RCS) of the Japan Proton Accelerator Research Complex (J-PARC) started its operation in 2007. The key functions of the LLRF control system are the dual harmonic auto…

Field-Programmable Gate Array (FPGA)-based Software-Defined Radio (SDR) is well-suited for experimenting with advanced wireless communication systems, as it allows to alter the architecture promptly while obtaining high performance.…

We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a…

We describe a modular multi-channel data acquisition system based on the 5-15 Gigasample-per-second waveform-recording PSEC4 chip. The system architecture incorporates two levels of hardware with FPGA-embedded system control and in-line…

Experiments in Atomic, Molecular, and Optical (AMO) physics require precise and accurate control of digital, analog, and radio frequency (RF) signals. We present a control hardware based on a field programmable gate array (FPGA) core which…