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While DETR-like architectures have demonstrated significant potential for monocular 3D object detection, they are often hindered by a critical limitation: the exclusion of 3D attributes from the bipartite matching process. This exclusion…
Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce…
Network-on-Chip (NoC) has become a popular choice for connecting a large number of processing cores in chip multiprocessor design. In a conventional NoC design, most of the area in the router is occupied by the buffers and the crossbar…
Multiresolution topology optimization (MTO) methods involve decoupling of the design and analysis discretizations, such that a high-resolution design can be obtained at relatively low analysis costs. Recent studies have shown that the MTO…
Composite materials are used across engineering applications for their superior mechanical performance, a result of efficient load transfer between the structure and matrix phases. However, the inherently two-dimensional structure of…
Device-to-device variability in experimental noise critically impacts reproducibility, especially in automated, high-throughput systems like additive manufacturing farms. While manageable in small labs, such variability can escalate into…
Thermal behavior has become a first-order constraint in advanced 2.5D/3D integrated circuits (ICs) and heterogeneous packages. As power densities rise and multiple active dies are vertically integrated, heat removal paths become…
Interfacial charge transfer (ICT) provides a powerful route to engineer electronic phases in correlated oxide heterostructures, yet predictive design principles remain elusive. Here, we systematically investigate superlattices composed of…
Topology optimization (TO) has been widely adopted in engineering design; however, it is prone to being trapped in local optima, particularly in strongly nonlinear problems. Sensitivity-free data-driven topology design (DDTD) offers a…
Theoretically, the three-dimensional (3D) array architecture provides a higher communication degree of freedom (DoF) compared to the planar arrays, allowing for greater capacity potential in multiple-input multiple-output (MIMO) systems.…
With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions -- one with ever-increasing connection density for better accuracy and the other with more compact sizing for energy…
The demand for the three-dimensional (3D) integration of electronic components is on a steady rise. The through-silicon-via (TSV) technique emerges as the only viable method for integrating single-crystalline device components in a 3D…
Enhancing the fracture toughness of diamond while preserving its hardness is a significant challenge. Traditional toughening strategies have primarily focused on modulating the internal microstructural units of diamonds, including…
A key challenge in on-chip interconnect design is to scale up bandwidth while maintaining low latency and high area efficiency. 2D-meshes scale with low wiring area and congestion overhead; however, their end-to-end latency increases with…
Network-on-chip (NoC) is a new aspect for designing of future System-On-Chips (SoC) where a vast number of IP cores are connected through interconnection network. The communication between the nodes occurred by routing packets rather than…
Many proposals to scale quantum technology rely on modular or distributed designs where individual quantum processors, called nodes, are linked together to form one large multinode quantum computer (MNQC). One scalable method to construct…
The ability to tune magnetic orders, such as magnetic anisotropy and topological spin texture, is desired in order to achieve high-performance spintronic devices. A recent strategy has been to employ interfacial engineering techniques, such…
In this paper, we present a reconfigurable hybrid Photonic-Plasmonic Network-on-Chip (NoC) based on the Dynamic Data Driven Application System (DDDAS) paradigm. In DDDAS computations and measurements form a dynamic closed feedback loop in…
LDPC (Low Density Parity Check) codes are among the most powerful and widely adopted modern error correcting codes. The iterative decoding algorithms required for these codes involve high computational complexity and high processing…
The transition to 4th generation district heating creates a growing need for scalable, automated design tools that accurately capture the spatial and temporal details of heating network operation. This paper presents an automated design…