Related papers: Design of TDC ASIC based on Temperature Compensati…
The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two…
Precise temperature measurement at micro/nanoscale is crucial across various domains including physical sciences, chemical processes, industrial production, medical diagnosis, weather forecasting, electronics, and biology. Micro/nanoscale…
The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the…
Here in this paper we are presenting a digital system background technique for correcting the time offset error rate and gain mismatches in a time interleaved analog to digital converter system for N channel communication using 8 bit…
Short Baseline Near Detector (SBND), which is a 260-ton LAr TPC as near detector in Short Baseline Neutrino (SBN) program, consists of 11,264 TPC readout channels. As an enabling technology for noble liquid detectors in neutrino…
This brief presents a technique for compensating the temperature coefficient (TC) of a bandgap reference (BGR) using temperature characteristics of transistor's current gain \b{eta}. As a comparison, three BGR circuits built with Si BJTs…
For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region to mitigate the effects of the increased pile-up. The chosen detection technology is Low…
We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been…
A Time to Digital Converter (TDC) based system, to be used for most sub-detectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital Trigger and Data AcQuisition system (TDAQ), in which the…
Integrated sensing and communication (ISAC) will greatly enhance the efficiency of physical resource utilization. The design of ISAC signal based on the orthogonal frequency division multiplex (OFDM) signal is the mainstream. However, when…
A decision feedback circuit with integrated offset compensation is presented in this paper. The circuit is built around the sense amplifier comparator. The feedback loop is closed around the first stage of the comparator resulting in…
A field programmable gate array (FPGA) based timing and trigger control system has been developed for the Dynamic Compression Sector (DCS) user facility located at the Advanced Photon Source (APS) at Argonne National Laboratory. The DCS is…
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance…
Time-domain nonvolatile in-memory computing (TD-nvIMC) offers a promising pathway to reduce data movement and improve energy efficiency by encoding computation in delay rather than voltage or current. This work presents a fully integrated…
This paper presents a fast impedance measurement IC for large-scale piezo-resistive sensor array. It features a unified differential time-to-digital demodulation architecture that readout impedance directly through the excitation circuit.…
Detectors based on pixels with timing capabilities are gaining increasing importance in the last years. Next-to-come high-energy physics experiments at colliders require the use of time information in tracking, due to the expected levels of…
Clock synchronization procedures are mandatory in most physical experiments where event fragments are readout by spatially dislocated sensors and must be glued together to reconstruct key parameters (e.g. energy, interaction vertex etc.) of…
Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a…
This paper presents a hardware architecture of fast simplified successive cancellation (fast-SSC) algorithm for polar codes, which significantly reduces the decoding latency and dramatically increases the throughput. Algorithmically,…
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on…