Related papers: Design of TDC ASIC based on Temperature Compensati…
This work presents the 8-channel FastIC+, a low-power consumption and highly configurable multi-channel front-end ASIC with internal digitization, for the readout of photo-sensors with picosecond time resolution and intrinsic gain. This…
Low-noise temperature measurements at frequencies in the milli-Hertz range are needed in the LISA and LISA PathFinder (LPF). The required temperature stability for LISA is around 10 uK/sqrt(Hz) at frequencies down to 0.1 mHz. In this paper…
We investigate experimentally a cascade of temperature-compensated unequal-path interferometers that can be used to measure frequency states in a high-dimensional quantum distribution system. In particular, we demonstrate that…
We present measurements with a GEM based TPC prototypes and the TimePix CMOS ASIC as charge collecting anode. Tests with a small prototype were performed in a 5 GeV electron beam at DESY. Different GEM orientations and geometries were…
In this contribution the emulation of an ASIC temperature and power monitoring system (TPMon) for FPGA prototyping is presented and tested to control processor temperatures under different control targets and operating strategies. The…
Timepix3 is a multi-purpose readout ASIC for hybrid pixel detectors. It can measure time and energy simultaneously by employing time-of-arrival (ToA) and time-over-threshold (ToT) techniques. Both methods are systematically affected by…
The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog…
The thermal sensitive electrical parameter (TSEP) method is crucial for enhancing the reliability of power devices through junction temperature monitoring. The TSEP method comprises three key processes: calibration, regression, and…
We present the design and characterization of the first full chain precision timing prototype ASIC, named ETL Readout Chip version 1 (ETROC1) for the CMS MTD endcap timing layer (ETL) upgrade. The ETL utilizes Low Gain Avalanche Diode…
We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC)…
An ADC is used to convert analog signals into binary signals. Compared with many other types of ADCs, flash converters are incredibly quick. A typical Flash ADC consists of 2n resistors, 2n-1 op-amp comparators, and an encoder which…
The timing performance of silicon sensors bump-bonded to Timepix3 ASICs is investigated, prior to and after different types of irradiation up to $8 \times 10^{15} 1 \mathrm{\,Me\kern -0.1em V} \mathrm{ \,n_{eq}} {\mathrm{ \,cm}}^{-2}$. The…
Time measurement plays a crucial rule for the purpose of particle identification in high energy physical experiments. With the upgrading of physical goal and the developing of electronics, modern time measurement system meets the…
We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) in the CDF Experiment at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each…
To overcome the limitations of conventional floating-point number formats, an interval arithmetic and variable-width storage format called universal number (unum) has been recently introduced. This paper presents the first (to the best of…
This brief proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture uses a novel branch metric unit specific to PAC codes. The proposed decoder is tested on…
The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 {\mu}m CMOS prototype device contains two channels and each channel employs a…
The SAMpler for PICosecond time (SAMPIC) chip has been designed by a collaboration including CEA/IRFU/SEDI, Saclay and CNRS/LAL/SERDI, Orsay. It benefits from both the quick response of a time to digital converter and the versatility of a…
We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end…
This work discusses the suitability of typical power line communication (PLC) pulses for fault sensing in power lines via pulse-compression time-domain reflectometry (TDR). For this purpose, we first carefully outline a TDR system operating…