Hardware Implementation of Fano Decoder for Polarization-adjusted Convolutional (PAC) Codes
Information Theory
2021-06-30 v3 Hardware Architecture
math.IT
Abstract
This brief proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture uses a novel branch metric unit specific to PAC codes. The proposed decoder is tested on FPGA, and its performance is evaluated on ASIC using TSMC 28 nm 0.72 V library. The decoder can be clocked at 500 MHz and reach an average information throughput of 38 Mb/s at 3.5 dB signal-to-noise ratio for a block length of 128 and a code rate of 1/2.
Cite
@article{arxiv.2011.09819,
title = {Hardware Implementation of Fano Decoder for Polarization-adjusted Convolutional (PAC) Codes},
author = {Amir Mozammel},
journal= {arXiv preprint arXiv:2011.09819},
year = {2021}
}