Related papers: Design of TDC ASIC based on Temperature Compensati…
In the last years, high-resolution time tagging has emerged as the tool to tackle the problem of high-track density in the detectors of the next generation of experiments at particle colliders. Time resolutions below 50ps and event average…
Targeting high-throughput and low-power communications, we implement two successive cancellation (SC) decoders for polar codes. With $16nm$ ASIC technology, the area efficiency and energy efficiency are $4Tbps/mm^2$ and $0.63pJ/bit$,…
As ASIC supply voltages approach one volt, the source-impedance goals for power distribution networks are driven ever lower as well. One approach to achieving these goals is to add decoupling capacitors of various values until the desired…
A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50…
In this paper the PreAmplifier ShAper (PASA) for the Time Projection Chamber (TPC) of the ALICE experiment at LHC is presented. The ALICE TPC PASA is an ASIC that integrates 16 identical channels, each consisting of Charge Sensitive…
The front-end electronics of silicon detectors are typically designed to ensure optimal noise performance for the expected input charge. A combination of preamplifiers and shaper circuits result in a nontrivial response of the front-end to…
Results of detailed simulations of the charge transfer inefficiency of a prototype serial readout CCD chip are reported. The effect of radiation damage on the chip operating in a particle detector at high frequency at a future accelerator…
The expanding instrumentation of processes throughout society with sensors yields a proliferation of time series data that may in turn enable important applications, e.g., related to transportation infrastructures or power grids.…
Convenience and safeguarding our home appliances have become an important issue when dealing with an advancement and growth of an economy. This research focuses on the design and construction of a Dual Sensor heat-monitoring system. The…
We propose a statistical mechanical framework to unify the observed relationship between the superconducting energy gap $\Delta$, the pseudogap $\Delta^\ast$, and the critical temperature $T_\mathrm{c}$. In this model, fermions couple as a…
Due to embedded systems` stringent design constraints, much prior work focused on optimizing energy consumption and/or performance. Since embedded systems typically have fewer cooling options, rising temperature, and thus temperature…
In this work, we have built an experimental setup to simulate the clock noise transmission with two spacecrafts and two optical links, and further demonstrated the extraction of picometer level signal drowned by the large laser frequency…
We report on the experimental study made on a successive prototype of High-Voltage CMOS (HV-CMOS) ATLASPix2 sensor for the tracking detector application, developed with 180 nm feature size. These sensors are to qualify mainly the peripheral…
Atomic clocks play a crucial role in timekeeping, communications, and navigation systems. Recent efforts enabled by heterogeneous MEMS integration have led to the commercial introduction of Chip-Scale Atomic Clocks (CSAC) with a volume of…
Thermal-Aware Scheduling (TAS) provides methods to manage the thermal dissipation of a computing chip during task execution. These methods aim to avoid issues such as accelerated aging of the device, premature failure and degraded chip…
We consider a robust stabilization of the fourth-order oscillatory systems with non-collocated output sensing. Worth recalling is that the fourth-order systems are relatively common in mechatronics as soon as there are two-mass or more…
This manuscript reports a semiconductor-sensitized thermal cell (STC) that converts ambient heat into electrical power while simultaneously reducing its own temperature under isothermal conditions. Using a printable…
The race towards performance increase and computing power has led to chips with heterogeneous and complex designs, integrating an ever-growing number of cores on the same monolithic chip or chiplet silicon die. Higher integration density,…
We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages to compensate the threshold voltage…
In recent years, Compute-in-memory (CiM) architectures have emerged as a promising solution for deep neural network (NN) accelerators. Multiply-accumulate~(MAC) is considered a {\textit de facto} unit operation in NNs. By leveraging the…