A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 {\mu}m thick epilayer of 350 {\Omega}cm resistivity were used to produce a fully depleted sensor. Laboratory and testbeam measurements of the analog channels present in the pixel matrix show that the sensor has a 130 V wide bias-voltage operation plateau at which the efficiency is 99.8%. Although this prototype does not include an internal gain layer, the design optimised for timing of the sensor and the front-end electronics provides a time resolutions of 20 ps.
@article{arxiv.2301.12244,
title = {20 ps Time Resolution with a Fully-Efficient Monolithic Silicon Pixel Detector without Internal Gain Layer},
author = {S. Zambito and M. Milanesio and T. Moretti and L. Paolozzi and M. Munker and R. Cardella and T. Kugathasan and F. Martinelli and A. Picardi and M. Elviretti and H. Rücker and A. Trusch and F. Cadoux and R. Cardarelli and S. Débieux and Y. Favre and C. A. Fenoglio and D. Ferrere and S. Gonzalez-Sevilla and L. Iodice and R. Kotitsa and C. Magliocca and M. Nessi and A. Pizarro-Medina and J. Sabater Iglesias and J. Saidi and M. Vicente Barreto Pinto and G. Iacobucci},
journal= {arXiv preprint arXiv:2301.12244},
year = {2023}
}