This paper presents the design and characterization of a monolithic integrated circuit (IC) including digital silicon photomultipliers (dSiPMs) arranged in a 32×32 pixel matrix at 70μm pitch. The IC provides per-quadrant time stamping and hit-map readout, and is fabricated in a standard 150-nm CMOS technology. Each dSiPM pixel consists of four single-photon avalanche diodes (SPADs) sharing a quenching and subsequent processing circuitry and has a fill factor of 30%. A sub-100ps precision, 12-bit time-to-digital converter (TDC) provides timestamps per quadrant with an acquisition rate of 3MHz. Together with the hit map, the total sustained data throughput of the IC amounts to 4Gbps. Measurements obtained in a dark, temperature-stable environment as well as by using a pulsed laser environment show the full dSiPM-IC functionality. The dark-count rate (DCR) as function of the overvoltage and temperature, the TDC resolution, differential and integral nonlinearity (DNL/INL) as well as the propagation-delay variations across the matrix are presented. With aid of additional peripheral test structures, the main building blocks are characterized and key parameters are presented.
@article{arxiv.2311.13220,
title = {Monolithic MHz-frame rate digital SiPM-IC with sub-100 ps precision and 70$~\mu$m pixel pitch},
author = {I. Diehl and K. Hansen and T. Vanat and G. Vignola and F. Feindt and D. Rastorguev and S. Spannagel},
journal= {arXiv preprint arXiv:2311.13220},
year = {2023}
}