Related papers: Si Nanowire - Array Source Gated Transistors

The cold source field-effect transistor (CSFET) is promising for reducing power dissipation in integrated circuits by engineering the density of states at the injecting source. Existing CSFET designs utilizing Dirac-source metals or…

Short channel (~80 nm) n-type single-walled carbon nanotube (SWNT) field-effect transistors (FETs) with potassium (K) doped source and drain regions and high-k gate dielectrics (ALD HfO2) are obtained. For nanotubes with diameter ~ 1.6 nm…

We investigate the operation of dual-gate reconfigurable field-effect transistor (RFET) in the programgate at drain (PGAD) and program-gate at source (PGAS) configurations. To this end, dual-gate silicon nanowire (SiNW) FETs are fabricated…

We report the fabrication of back-gated field-effect transistors (FETs) using ultra-thin, mechanically exfoliated MoSe2 flakes. The MoSe2 FETs are n-type and possess a high gate modulation, with On/Off ratios larger than 106. The devices…

Spin-gapless semiconductors (SGSs) are a promising class of materials for spintronic applications, enabling functions beyond conventional electronics. This study introduces a novel design for multifunctional spintronic field-effect…

Junctionless transistors made of silicon have previously been demonstrated experimentally and by simulations. Junctionless devices do not require fabricating an abrupt source-drain junction and thus can be easier to implement in aggressive…

Bottom-up synthesized GNRs and GNR heterostructures have promising electronic properties for high performance field effect transistors (FETs) and ultra-low power devices such as tunnelling FETs. However, the short length and wide band gap…

The self-heating effect is a severe issue for high-power semiconductor devices, which degrades the electron mobility and saturation velocity, and also affects the device reliability. On applying an ultrafast and high-resolution…

We present a theoretical framework for the calculation of charge transport through nanowire-based Schottky-barrier field-effect transistors that is conceptually simple but still captures the relevant physical mechanisms of the transport…

We investigate the low temperature transport in 8 nm diameter Si junctionless nanowire field effect transistors fabricated by top down techniques with a wrap-around gate and two different activated doping densities. First we extract the…

High performance enhancement mode semiconducting carbon nanotube field-effect transistors (CNTFETs) are obtained by combining ohmic metal-tube contacts, high dielectric constant HfO2 films as gate insulators, and electrostatically doped…

Gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is a promising device architecture due to its superior gate controllability than that of the conventional FinFET architecture. The significantly higher electron mobility of…

In this study, a model of a Schottky-barrier carbon nanotube field- effect transistor (CNT-FET), with ferromagnetic contacts, has been developed. The emphasis is put on analysis of current-voltage characteristics as well as shot (and…

Density functional theory and molecular dynamics simulations have been used to optimize the structure of nanowires of SiO2. The starting structures were based on b-cristobalite, orthotridymite, b-tridymite, and rutile crystals. The analysis…

Gate tunable p-type multilayer tin mono-sulfide (SnS) field-effect transistor (FET) devices with SnS thickness between 50 and 100 nm were fabricated and studied to understand their performances. The devices showed anisotropic inplane…

In this article, a novel two-path model is proposed to quantitatively explain sub-threshold characteristics of back-gated Schottky barrier FETs (SB-FETs) from 2D channel materials. The model integrates the 'conventional' model for SB-FETs…

Quantized conductance is reported in high-crystalline tin oxide (SnO2) nanobelt back-gate field-effect transistors, at low temperatures. The quantized conductance was observed as current oscillations in the drain current vs. gate voltage…

We investigate the mechanisms responsible for the low-frequency noise in liquid-gated nano-scale silicon nanowire field-effect transistors (SiNW-FETs) and show that the charge-noise level is lower than elementary charge. Our measurements…

Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform predictive first-principles simulations of junctionless gated Si nanowire transistors. Our primary predictions are…

Nano-membrane tri-gate beta-gallium oxide (\b{eta}-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized…