Related papers: Si Nanowire - Array Source Gated Transistors
High performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (Lch) down to 20nm have been fabricated by integrating a higher-k LaAlO3-based gate stack with an equivalent oxide thickness of 1.2nm. It is found that…
Exploration of new dielectrics with large capacitive coupling is an essential topic in modern electronics when conventional dielectrics suffer from the leakage issue near breakdown limit. To address this looming challenge, we demonstrate…
We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator…
We present the findings of the superconductivity in the silicon nanostructures prepared by short time diffusion of boron after preliminary oxidation of the n-type Si (100) surface. These Si-based nanostructures represent the p-type high…
Contacts between high critical field superconductors and semiconductor nanowires are important in the context of topological quantum circuits in which superconductivity must be sustained to high magnetic fields. Here we demonstrate…
We propose a new orbital controlled model to explain the gate field induced switching of current in a semiconducting PbS-nanowire junction. A single particle scattering formalism in conjunction with a posteriori density functional approach…
InAs nanowires have been actively explored as the channel material for high performance transistors owing to their high electron mobility and ease of ohmic metal contact formation. The catalytic growth of non-epitaxial InAs nanowires,…
Thin film transistors (TFTs) made of transparent channel semiconductors such as ZnO are of great technological importance, because their insensitivity to visible light makes device structures simple. In fact, several demonstrations are made…
A low Schottky barrier height (SBH) at source/drain contact is essential for achieving high drive current in atomic layer MoS2 channel based field-effect transistors. Approaches such as choosing metals with appropriate work functions and…
Two-dimensional MoS2 has emerged as promising material for nanoelectronics and spintronics due to its exotic properties. However, high contact resistance at metal semiconductor MoS2 interface still remains an open issue. Here, we report…
Top-gated, few-layer graphene field-effect transistors (FETs) fabricated on thermally-decomposed semi-insulating 4H-SiC substrates are demonstrated. Physical vapor deposited SiO2 is used as the gate dielectric. A two-dimensional hexagonal…
We investigate transport through ionic liquid gated field effect transistors (FETs) based on exfoliated crystals of semiconducting WS$_2$. Upon electron accumulation, at surface densities close to -or just larger than- 10$^{14}$ cm$^{-2}$,…
As silicon transistors scale toward future technology nodes, three-dimensional architectures -- including gate-all-around (GAA) nanoribbon and complementary field-effect transistors (CFETs) -- require channel widths in the tens of…
Group IV Ge1-xSnx semiconductors hold the premise of enabling broadband silicon-integrated infrared optoelectronics due to their tunable bandgap energy and directness. Herein, we exploit these attributes along with the enhanced lattice…
We consider nanowires in the field effect transistor device configuration. Modeling each nanowire as a one dimensional lattice with random site potentials, we study the heat exchanges between the nanowire electrons and the substrate…
In this paper, we have experimentally demonstrated, for the first time, III-V 4D transistors with vertically stacked InGaAs nanowire (NW) channels and gate-all-around (GAA) architecture. Novel process technology enabling the transition from…
Doping is a common route to reducing nanowire transistor on-resistance but has limits. High doping level gives significant loss in gate performance and ultimately complete gate failure. We show that electrolyte gating remains effective even…
We fabricate and characterize dual-gated graphene field-effect transistors (FETs) using Al2O3 as top-gate dielectric. We use a thin Al film as a nucleation layer to enable the atomic layer deposition of Al2O3. Our devices show mobility…
High-performance single-wall carbon nanotube field-effect transistors (SWNT-FETs) are fabricated using directed assembly and mass-produced carbon nanotubes (CNTs). These FETs exhibit operating characteristics comparable to state-of-the-art…
An evaluation of the gate capacitance of a field-effect transitor (FET) whose channel length and width are several ten nanometer, is a key point for sensors applications. However, experimental and precise evaluation of capacitance in the aF…