We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm2 is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a Current Spin Density Functional Theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronics and quantum variables based devices.
@article{arxiv.1203.4811,
title = {Few Electron Limit of n-type Metal Oxide Semiconductor Single Electron Transistors},
author = {Enrico Prati and Marco De Michielis and Matteo Belli and Simone Cocco and Marco Fanciulli and Dharmraj Kotekar-Patil and Matthias Ruoff and Dieter P. Kern and David A. Wharam and Arjan Verduijn and Giuseppe Tettamanzi and Sven Rogge and Benoit Roche and Romain Wacquez and Xavier Jehl and Maud Vinet and Marc Sanquer},
journal= {arXiv preprint arXiv:1203.4811},
year = {2015}
}