Related papers: Si Nanowire - Array Source Gated Transistors

Understanding of the electrical contact properties of semiconductor nanowire (NW) field effect transistors (FETs) plays a crucial role in employing semiconducting NWs as building blocks for future nanoelectronic devices and in the study of…

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire…

We report on the electronic transport properties of multiple-gate devices fabricated from undoped silicon nanowires. Understanding and control of the relevant transport mechanisms was achieved by means of local electrostatic gating and…

In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our…

In this study, InSb nanowires have been formed by electrodeposition and integrated into NW-FETs. NWs were formed in porous anodic alumina (PAA) templates, with the PAA pore diameter of approximately 100 nm defining the NW diameter.…

We demonstrate a top-down fabricated reconfigurable field effect transistor (RFET) based on a silicon nanowire that can be electrostatically programmed to p- and n-configuration. The device unites a high symmetry of transfer…

Silicon nanowires (Si NW) are ideal candidates for solution processable field effect transistors (FETs). The interface between the nanowire channel and the gate dielectric plays a crucial role in the FET performance, and it can be…

An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for…

Nominally undoped silicon nanowires (NW) were grown by catalytic chemical vapor deposition. The growth process was optimized to control the NWs diameters by using different Au catalyst thicknesses on amorphous SiO2, Si3N4, or crystalline-Si…

As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits; many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has…

Gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology node. In particular, the junctionless nanowire transistors…

Single-walled carbon nanotubes (SWNTs) have been grown via chemical vapor deposition on high-kappa dielectric SrTiO3/Si substrates, and high-performance semiconducting SWNT field-effect transistors have been fabricated using the thin SrTiO3…

We report the realization of field-effect transistors (FETs) made with chemically- synthesized layered two dimensional (2D) crystal semiconductor WS2. The 2D Schottky-barrier FETs demonstrate ambipolar behavior and a high (~105x) on/off…

High performance p- and n-type single-walled carbon nanotube (SWNT) field-effect transistors (FETs) are obtained by using high and low work function metals, Pd and Al as source/drain (S/D) electrodes respectively. Ohmic contacts made to…

We analyze the performance of a recently reported Ge/Si core/shell nanowire transistor using a semiclassical, ballistic transport model and an sp3s*d5 tight-binding treatment of the electronic structure. Comparison of the measured…

We investigate electronic transport properties of Schottky-barrier field-effect transistors (FET) based on double-walled carbon nanotubes (DWNT) with a semiconducting outer shell and a metallic inner one. These kind of DWNT-FET show…

Substantial progress on field effect transistors "FETs" consisting of semiconducting single wall carbon nanotubes "s-SWNTs" without detectable traces of metallic nanotubes and impurities is reported. Nearly perfect removal of metallic…

Gate capacitances of back-gated nanowire field-effect transistors (NW-FETs) are calculated by means of finite element methods and the results are compared with analytical results of the ``metallic cylinder on an infinite metal plate…

We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned…

Achieving high crystalline quality Ge$_{1-x}$Sn$_{x}$ semiconductors at Sn content exceeding 10\% is quintessential to implementing the long sought-after silicon-compatible mid-infrared photonics. Herein, by using sub-20 nm Ge nanowires as…