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Nanofabricated metal gate electrodes are commonly used to confine and control electrons in electrostatically defined quantum dots. However, these same gates impart strain-induced potential fluctuations that can potentially impair device…
In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the…
Nano-membrane tri-gate beta-gallium oxide (\b{eta}-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized…
In this work, quantum ballistic simulation study of a III-V tri-gate MOSFET has been presented. At the same time, effects of device parameter variation on ballistic, subthrshold and short channel performance is observed and presented. The…
Fully depleted (FD) Silicon on Insulator (SOI) metal oxide Field Effect Transistor (MOSFET) Is the Leading Contender for Sun 65nm Regime. This paper presents a study of effects of work functions of metal gate on the performance of FD-SOI…
Gate-All-Around Field-Effect Transistors (GAAFETs), now entering high-volume production as successors to fin field-effect transistor technology, are enabling continued scaling and enhanced performance in advanced semiconductor nodes.…
Scalable methods for improving the performance and stability of a field-effect transistor (FET) based on two-dimensional materials are crucial for its real applications. A scalable method of encapsulating the exfoliated MoS$ _{2} $ on SiO$…
Vertical field effect transistors (VFETs) show many advantages such as high switching speed, low operating voltage, low power consumption, and miniaturization over lateral FETs. However, VFET still faces the main challenges of high…
Metals are commonly used as electrostatic gates in devices due to their abundant charge carrier densities that are necessary for efficient charging and discharging. A semiconducting gate can be beneficial for certain fabrication processes,…
In this article, we investigate electrical transport properties in ultrathin body (UTB) MoS2 two-dimensional (2D) crystals with channel lengths ranging from 2 {\mu}m down to 50 nm. We compare the short channel behavior of sets of MOSFETs…
The tremendous progress in Metal Oxide Semiconductor (MOS) technology has been a direct consequence of device scaling for past several decades. But as we have entered the nanometer era many problems related to leakage currents and other…
In recent years, a lot of scientific research effort has been put forth for the investigation of Transition Metal Dichalcogenides (TMDC) and other Two Dimensional (2D) materials like Graphene, Boron Nitride. Theoretical investigation on the…
TiO2 ferroelectric field effect transistors (FeFETs) with HfZrO2 (HZO) ferroelectric dielectric layers and bottom gate topology are fabricated for applications in neuromorphic systems. Two sets of devices are fabricated with different gate…
A common issue in low temperature measurements of enhancement-mode metal-oxide-semiconductor (MOS) field-effect transistors (FETs) in the low electron density regime is the high contact resistance dominating the device impedance. In that…
In this paper, 20nm - 80nm channel length (Lch) InGaAs gate- all-around (GAA) nanowire MOSFETs with record high on- state and off-state performance have been demonstrated by equivalent oxide thickness (EOT) and nanowire width (WNW) scaling…
Multiple-gate SOI MOSFETs with gate length equal to 25 nm are compared using device Monte Carlo simulation. In such architectures, the short channel effects may be controlled with much less stringent body and oxide thickness requirements…
Large capacitance enhancement is useful for increasing the gate capacitance of field-effect transistors (FETs) to produce low-energy-consuming devices with improved gate controllability. We report strong capacitance enhancement effects in a…
Thanks to their unique properties single-layer 2-D materials appear as excellent candidates to extend Moore's scaling law beyond the currently manufactured silicon FinFETs. However, the known 2-D semiconducting components, essentially…
We study the impact of top SiO2 interlayer thickness on memory window of Si channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. The memory window increases with thicker top SiO2. We realize the memory window of 6.3 V…
We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range 7-17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding,…