Related papers: Optimum High-k Oxide for the Best Performance of U…
The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve…
In this letter, we report on high performance depletion/enhancement (D/E)-mode beta-Ga2O3 on insulator (GOOI) field-effect transistors (FETs) with record high drain currents (ID) of 600/450 mA/mm, which are nearly one order of magnitude…
We fabricate planar all-graphene field-effect transistors with self-aligned side-gates at 100 nm from the main graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1V with conductance modulation of…
The structure property of non-ideal Si/GaAs heterostructures that were integrated with the ultra-thin oxide (UO) tunneling interfacial layer has been systematically investigated. Si nanomembranes (NMs) were oxidized in different time…
MoS$_2$ field-effect transistors (FETs) with high-\textit{k} oxides currently lag behind silicon standards in bias and temperature stability due to ubiquitous border oxide traps that cause clockwise (CW) hysteresis in gate transfer…
Top-gated, few-layer graphene field-effect transistors (FETs) fabricated on thermally-decomposed semi-insulating 4H-SiC substrates are demonstrated. Physical vapor deposited SiO2 is used as the gate dielectric. A two-dimensional hexagonal…
Variational quantum algorithms are believed to be promising for solving computationally hard problems and are often comprised of repeated layers of quantum gates. An example thereof is the quantum approximate optimization algorithm (QAOA),…
Transistor miniaturization requires controlling gate leakage through ultrathin dielectrics and minimizing source/drain contact resistance. Although two-dimensional (2D) semiconductors offer excellent electrostatic control, their interfaces…
The possibility of optimization of high voltage hybrid SIT-MOS transistors (HSMT) by local reduction of the lifetime near anode emitter and/or reduction of the anode emitter injection ability by three different ways has been investigated…
We study the channel width scaling of back-gated MoS2 metal-oxide-semiconductor field-effect transistors (MOSFETs) from 2 {\mu}m down to 60 nm. We reveal that the channel conductance scales linearly with channel width, indicating no evident…
Aluminum oxide (Al2O3) has been grown by atomic layer deposition on n-type 4H-SiC with and without a thin silicon dioxide (SiO2) intermediate layer. By means of Capacitance Voltage and Thermal Dielectric Relaxation Current measurements, the…
Ambipolar dual-gate transistors based on two-dimensional (2D) materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with suppressed…
We introduce a deep-recessed gate architecture in $\beta$-Ga$_2$O$_3$ delta-doped field effect transistors for improvement in DC-RF dispersion and breakdown properties. The device design incorporates an unintentionally doped…
We found that the conductivity of the two-dimensional electron system in Si-MOS structures is limited to a maximum value, G_{max}, as either density increases or temperature decreases. This value G_{max} is weakly disorder dependent and…
A dual-gate graphene field-effect transistors is presented, which shows improved RF performance by reducing the access resistance using electrostatic doping. With a carrier mobility of 2700 cm2/Vs, a cutoff frequency of 50 GHz is…
Surface oxides are associated with two-level systems (TLSs) that degrade the performance of niobium-based superconducting quantum computing devices. To address this, we introduce a predictive framework for selecting metal capping layers…
The formation of hafnium silicate films (HfSixOy) for use as gate oxides with large dielectric constant by solid state reaction of Hf metal and SiO2 was investigated. Thin, fully reacted silicate films could be formed, and were thermally…
Quantization in the inversion layer and phase coherent transport are anticipated to have significant impact on device performance in 'ballistic' nanoscale transistors. While the role of some quantum effects have been analyzed qualitatively…
The integration of high-k dielectrics with two-dimensional (2D) semiconductors is a critical step towards high-performance nanoelectronics, which however remains challenging due to high density of interface states and the damage to the…
Enhancement-mode Si/SiGe electron quantum dots have been pursued extensively by many groups for \revEdit{their} potential in quantum computing. Most of the reported dot designs utilize multiple metal-gate layers and use Si/SiGe…