Transistor miniaturization requires controlling gate leakage through ultrathin dielectrics and minimizing source/drain contact resistance. Although two-dimensional (2D) semiconductors offer excellent electrostatic control, their interfaces with gate dielectrics and contact metals often form a van der Waals (vdW) gap that impacts device performance and acts as a tunneling barrier with a low-dielectric constant. While this reduces dielectric leakage, it increases metal-channel contact resistance and introduces a parasitic series capacitance to the gate. We quantified the trade-off between leakage suppression and electrostatic and contact-resistance scaling limits. As a result, many insulators fail to meet scaling targets, and metal-channel contacts fall short of required resistances. Zipper-like interfaces, where quasi-covalent bonding removes the vdW gap without creating dangling bonds, offer a path toward ultrascaled transistor designs.
@article{arxiv.2509.17617,
title = {Device-scaling constraints imposed by the van der Waals gap formed in two-dimensional materials},
author = {Mahdi Pourfath and Tibor Grasser},
journal= {arXiv preprint arXiv:2509.17617},
year = {2026}
}